Lines Matching refs:u8
33 u8 ref_clock;
34 u8 settling_time;
35 u8 clk_valid_on_wakeup;
36 u8 dc2dc_mode;
37 u8 dual_mode_select;
38 u8 tx_bip_fem_auto_detect;
39 u8 tx_bip_fem_manufacturer;
40 u8 general_settings;
41 u8 sr_state;
42 u8 srf1[WL1271_INI_MAX_SMART_REFLEX_PARAM];
43 u8 srf2[WL1271_INI_MAX_SMART_REFLEX_PARAM];
44 u8 srf3[WL1271_INI_MAX_SMART_REFLEX_PARAM];
50 u8 ref_clock;
51 u8 settling_time;
52 u8 clk_valid_on_wakeup;
53 u8 tcxo_ref_clock;
54 u8 tcxo_settling_time;
55 u8 tcxo_valid_on_wakeup;
56 u8 tcxo_ldo_voltage;
57 u8 xtal_itrim_val;
58 u8 platform_conf;
59 u8 dual_mode_select;
60 u8 tx_bip_fem_auto_detect;
61 u8 tx_bip_fem_manufacturer;
62 u8 general_settings[WL128X_INI_MAX_SETTINGS_PARAM];
63 u8 sr_state;
64 u8 srf1[WL1271_INI_MAX_SMART_REFLEX_PARAM];
65 u8 srf2[WL1271_INI_MAX_SMART_REFLEX_PARAM];
66 u8 srf3[WL1271_INI_MAX_SMART_REFLEX_PARAM];
72 u8 rx_trace_insertion_loss;
73 u8 tx_trace_loss;
74 u8 rx_rssi_process_compens[WL1271_INI_RSSI_PROCESS_COMPENS_SIZE];
80 u8 rx_trace_insertion_loss;
81 u8 tx_trace_loss[WL1271_INI_CHANNEL_COUNT_2];
82 u8 rx_rssi_process_compens[WL1271_INI_RSSI_PROCESS_COMPENS_SIZE];
89 u8 tx_bip_ref_power;
90 u8 tx_bip_ref_offset;
91 u8 tx_per_rate_pwr_limits_normal[WL1271_INI_RATE_GROUP_COUNT];
92 u8 tx_per_rate_pwr_limits_degraded[WL1271_INI_RATE_GROUP_COUNT];
93 u8 tx_per_rate_pwr_limits_extreme[WL1271_INI_RATE_GROUP_COUNT];
94 u8 tx_per_chan_pwr_limits_11b[WL1271_INI_CHANNEL_COUNT_2];
95 u8 tx_per_chan_pwr_limits_ofdm[WL1271_INI_CHANNEL_COUNT_2];
96 u8 tx_pd_vs_rate_offsets[WL1271_INI_RATE_GROUP_COUNT];
97 u8 tx_ibias[WL1271_INI_RATE_GROUP_COUNT];
98 u8 rx_fem_insertion_loss;
99 u8 degraded_low_to_normal_thr;
100 u8 normal_to_degraded_high_thr;
109 u8 tx_bip_ref_power;
110 u8 tx_bip_ref_offset;
111 u8 tx_per_rate_pwr_limits_normal[WL128X_INI_RATE_GROUP_COUNT];
112 u8 tx_per_rate_pwr_limits_degraded[WL128X_INI_RATE_GROUP_COUNT];
113 u8 tx_per_rate_pwr_limits_extreme[WL128X_INI_RATE_GROUP_COUNT];
114 u8 tx_per_chan_pwr_limits_11b[WL1271_INI_CHANNEL_COUNT_2];
115 u8 tx_per_chan_pwr_limits_ofdm[WL1271_INI_CHANNEL_COUNT_2];
116 u8 tx_pd_vs_rate_offsets[WL128X_INI_RATE_GROUP_COUNT];
117 u8 tx_ibias[WL128X_INI_RATE_GROUP_COUNT + 1];
118 u8 tx_pd_vs_chan_offsets[WL1271_INI_CHANNEL_COUNT_2];
119 u8 tx_pd_vs_temperature[WL128X_INI_PD_VS_TEMPERATURE_RANGES];
120 u8 rx_fem_insertion_loss;
121 u8 degraded_low_to_normal_thr;
122 u8 normal_to_degraded_high_thr;
129 u8 rx_trace_insertion_loss[WL1271_INI_SUB_BAND_COUNT_5];
130 u8 tx_trace_loss[WL1271_INI_SUB_BAND_COUNT_5];
131 u8 rx_rssi_process_compens[WL1271_INI_RSSI_PROCESS_COMPENS_SIZE];
135 u8 rx_trace_insertion_loss[WL1271_INI_SUB_BAND_COUNT_5];
136 u8 tx_trace_loss[WL1271_INI_CHANNEL_COUNT_5];
137 u8 rx_rssi_process_compens[WL1271_INI_RSSI_PROCESS_COMPENS_SIZE];
142 u8 tx_bip_ref_power[WL1271_INI_SUB_BAND_COUNT_5];
143 u8 tx_bip_ref_offset[WL1271_INI_SUB_BAND_COUNT_5];
144 u8 tx_per_rate_pwr_limits_normal[WL1271_INI_RATE_GROUP_COUNT];
145 u8 tx_per_rate_pwr_limits_degraded[WL1271_INI_RATE_GROUP_COUNT];
146 u8 tx_per_rate_pwr_limits_extreme[WL1271_INI_RATE_GROUP_COUNT];
147 u8 tx_per_chan_pwr_limits_ofdm[WL1271_INI_CHANNEL_COUNT_5];
148 u8 tx_pd_vs_rate_offsets[WL1271_INI_RATE_GROUP_COUNT];
149 u8 tx_ibias[WL1271_INI_RATE_GROUP_COUNT];
150 u8 rx_fem_insertion_loss[WL1271_INI_SUB_BAND_COUNT_5];
151 u8 degraded_low_to_normal_thr;
152 u8 normal_to_degraded_high_thr;
157 u8 tx_bip_ref_power[WL1271_INI_SUB_BAND_COUNT_5];
158 u8 tx_bip_ref_offset[WL1271_INI_SUB_BAND_COUNT_5];
159 u8 tx_per_rate_pwr_limits_normal[WL128X_INI_RATE_GROUP_COUNT];
160 u8 tx_per_rate_pwr_limits_degraded[WL128X_INI_RATE_GROUP_COUNT];
161 u8 tx_per_rate_pwr_limits_extreme[WL128X_INI_RATE_GROUP_COUNT];
162 u8 tx_per_chan_pwr_limits_ofdm[WL1271_INI_CHANNEL_COUNT_5];
163 u8 tx_pd_vs_rate_offsets[WL128X_INI_RATE_GROUP_COUNT];
164 u8 tx_ibias[WL128X_INI_RATE_GROUP_COUNT];
165 u8 tx_pd_vs_chan_offsets[WL1271_INI_CHANNEL_COUNT_5];
166 u8 tx_pd_vs_temperature[WL1271_INI_SUB_BAND_COUNT_5 *
168 u8 rx_fem_insertion_loss[WL1271_INI_SUB_BAND_COUNT_5];
169 u8 degraded_low_to_normal_thr;
170 u8 normal_to_degraded_high_thr;
181 u8 nvs[WL1271_INI_NVS_SECTION_SIZE];
185 u8 padding1;
187 u8 padding2;
190 u8 padding;
193 u8 padding3;
196 u8 padding;
202 u8 nvs[WL1271_INI_NVS_SECTION_SIZE];
206 u8 fem_vendor_and_options;
208 u8 padding2;
211 u8 padding;
214 u8 padding3;
217 u8 padding;