Lines Matching defs:rtl_phy

839 struct rtl_phy {  struct
840 	struct bb_reg_def phyreg_def[4];	/*Radio A/B/C/D */
841 	struct init_gain initgain_backup;
842 	enum io_type current_io_type;
844 	u8 rf_mode;
845 	u8 rf_type;
846 	u8 current_chan_bw;
847 	u8 set_bwmode_inprogress;
848 	u8 sw_chnl_inprogress;
849 	u8 sw_chnl_stage;
850 	u8 sw_chnl_step;
851 	u8 current_channel;
852 	u8 h2c_box_num;
853 	u8 set_io_inprogress;
854 	u8 lck_inprogress;
857 	s32 reg_e94;
858 	s32 reg_e9c;
859 	s32 reg_ea4;
860 	s32 reg_eac;
861 	s32 reg_eb4;
862 	s32 reg_ebc;
863 	s32 reg_ec4;
864 	s32 reg_ecc;
865 	u8 rfpienable;
866 	u8 reserve_0;
867 	u16 reserve_1;
868 	u32 reg_c04, reg_c08, reg_874;
869 	u32 adda_backup[16];
870 	u32 iqk_mac_backup[IQK_MAC_REG_NUM];
871 	u32 iqk_bb_backup[10];
874 	bool need_iqk;
875 	struct iqk_matrix_regs iqk_matrix_regsetting[IQK_MATRIX_SETTINGS_NUM];
877 	bool rfpi_enable;
879 	u8 pwrgroup_cnt;
880 	u8 cck_high_power;
882 	u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
883 	u8 default_initialgain[4];
886 	u8 cur_cck_txpwridx;
887 	u8 cur_ofdm24g_txpwridx;
889 	u32 rfreg_chnlval[2];
890 	bool apk_done;
891 	u32 reg_rf3c[2];	/* pathA / pathB  */
894 	u8 framesync;
895 	u32 framesync_c34;
897 	u8 num_total_rfpath;
898 	struct phy_parameters hwparam_tables[MAX_TAB];
899 	u16 rf_pathmap;