Lines Matching refs:SCD_BASE
219 #define SCD_BASE (PRPH_BASE + 0xa02c00) macro
221 #define SCD_SRAM_BASE_ADDR (SCD_BASE + 0x0)
222 #define SCD_DRAM_BASE_ADDR (SCD_BASE + 0x8)
223 #define SCD_AIT (SCD_BASE + 0x0c)
224 #define SCD_TXFACT (SCD_BASE + 0x10)
225 #define SCD_ACTIVE (SCD_BASE + 0x14)
226 #define SCD_QUEUECHAIN_SEL (SCD_BASE + 0xe8)
227 #define SCD_CHAINEXT_EN (SCD_BASE + 0x244)
228 #define SCD_AGGR_SEL (SCD_BASE + 0x248)
229 #define SCD_INTERRUPT_MASK (SCD_BASE + 0x108)
234 return SCD_BASE + 0x18 + chnl * 4; in SCD_QUEUE_WRPTR()
236 return SCD_BASE + 0x284 + (chnl - 20) * 4; in SCD_QUEUE_WRPTR()
242 return SCD_BASE + 0x68 + chnl * 4; in SCD_QUEUE_RDPTR()
244 return SCD_BASE + 0x2B4 + (chnl - 20) * 4; in SCD_QUEUE_RDPTR()
250 return SCD_BASE + 0x10c + chnl * 4; in SCD_QUEUE_STATUS_BITS()
252 return SCD_BASE + 0x384 + (chnl - 20) * 4; in SCD_QUEUE_STATUS_BITS()