Lines Matching refs:b43_phy_mask
222 b43_phy_mask(dev, B43_LPPHY_AFE_DAC_CTL, 0xF7FF); in lpphy_baseband_rev0_1_init()
236 b43_phy_mask(dev, B43_LPPHY_RX_RADIO_CTL, 0xFFFE); in lpphy_baseband_rev0_1_init()
343 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF); in lpphy_baseband_rev0_1_init()
345 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0x7FFF); in lpphy_baseband_rev0_1_init()
346 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFBF); in lpphy_baseband_rev0_1_init()
432 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000); in lpphy_baseband_rev2plus_init()
433 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000); in lpphy_baseband_rev2plus_init()
447 b43_phy_mask(dev, B43_LPPHY_GAINDIRECTMISMATCH, ~0xF); in lpphy_baseband_rev2plus_init()
481 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF); in lpphy_baseband_rev2plus_init()
483 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x40); in lpphy_baseband_rev2plus_init()
690 b43_phy_mask(dev, B43_LPPHY_FOURWIRE_CTL, 0xFFFD); in lpphy_radio_init()
775 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFB); in lpphy_disable_crs()
777 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFF7); in lpphy_disable_crs()
781 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFDF); in lpphy_disable_crs()
783 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFBF); in lpphy_disable_crs()
787 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F); in lpphy_disable_crs()
789 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFDFF); in lpphy_disable_crs()
793 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFBFF); in lpphy_disable_crs()
794 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xF7FF); in lpphy_disable_crs()
803 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFF80); in lpphy_restore_crs()
804 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFC00); in lpphy_restore_crs()
811 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFE); in lpphy_disable_rx_gain_override()
812 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFEF); in lpphy_disable_rx_gain_override()
813 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFBF); in lpphy_disable_rx_gain_override()
815 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF); in lpphy_disable_rx_gain_override()
817 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFBFF); in lpphy_disable_rx_gain_override()
818 b43_phy_mask(dev, B43_PHY_OFDM(0xE5), 0xFFF7); in lpphy_disable_rx_gain_override()
821 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFDFF); in lpphy_disable_rx_gain_override()
844 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF); in lpphy_disable_tx_gain_override()
846 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFF7F); in lpphy_disable_tx_gain_override()
847 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xBFFF); in lpphy_disable_tx_gain_override()
849 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFBF); in lpphy_disable_tx_gain_override()
985 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFD); in lpphy_stop_ddfs()
986 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xFFDF); in lpphy_stop_ddfs()
993 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0xFF80); in lpphy_run_ddfs()
994 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0x80FF); in lpphy_run_ddfs()
1000 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFB); in lpphy_run_ddfs()
1010 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFF7); in lpphy_rx_iq_est()
1013 b43_phy_mask(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFEFF); in lpphy_rx_iq_est()
1054 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE); in lpphy_loopback()
1182 b43_phy_mask(dev, B43_PHY_OFDM(0xD0), 0xFFFD); in lpphy_set_tx_power_control()
1441 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x83FF); in b43_lpphy_op_software_rfkill()
1443 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0x80FF); in b43_lpphy_op_software_rfkill()
1444 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xDFFF); in b43_lpphy_op_software_rfkill()
1447 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xE0FF); in b43_lpphy_op_software_rfkill()
1449 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFCFF); in b43_lpphy_op_software_rfkill()
1453 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xE0FF); in b43_lpphy_op_software_rfkill()
1455 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xF7F7); in b43_lpphy_op_software_rfkill()
1457 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFFE7); in b43_lpphy_op_software_rfkill()
1484 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFC7); in lpphy_set_tssi_mux()
1512 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xEFFF); in lpphy_tx_pctl_init_hw()
1515 b43_phy_mask(dev, B43_PHY_OFDM(0x103), 0xFFFE); in lpphy_tx_pctl_init_hw()
1522 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xFF); in lpphy_tx_pctl_init_hw()
1527 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xF8FF); in lpphy_tx_pctl_init_hw()
1534 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xEFFF); in lpphy_tx_pctl_init_hw()
1547 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF); in lpphy_tx_pctl_init_hw()
1726 b43_phy_mask(dev, B43_LPPHY_RX_COMP_COEFF_S, 0x00FF); in lpphy_calc_rx_iq_comp()
1825 b43_phy_mask(dev, B43_LPPHY_SMPL_PLAY_COUNT, 0xF000); in lpphy_stop_tx_tone()
1933 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFFE); in lpphy_rx_iq_cal()
1934 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE); in lpphy_rx_iq_cal()
1946 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFC); in lpphy_rx_iq_cal()
1947 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFF7); in lpphy_rx_iq_cal()
1948 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFDF); in lpphy_rx_iq_cal()
1956 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFFE); in lpphy_rx_iq_cal()
1957 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xF7FF); in lpphy_rx_iq_cal()
2705 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xfff8); in b43_lpphy_op_switch_analog()