Lines Matching refs:u8
278 u8 opCapFlags;
279 u8 eepMisc;
281 u8 macAddr[6];
282 u8 rxMask;
283 u8 txMask;
288 u8 deviceType;
289 u8 pwdclkind;
290 u8 fastClk5g;
291 u8 divChain;
292 u8 rxGainType;
293 u8 dacHiPwrMode_5G;
294 u8 openLoopPwrCntl;
295 u8 dacLpMode;
296 u8 txGainType;
297 u8 rcChainMask;
298 u8 desiredScaleCCK;
299 u8 pwr_table_offset;
300 u8 frac_n_5g;
301 u8 futureBase_3[21];
308 u8 opCapFlags;
309 u8 eepMisc;
311 u8 macAddr[6];
312 u8 rxMask;
313 u8 txMask;
318 u8 deviceType;
319 u8 txGainType;
325 u8 spurRangeLow;
326 u8 spurRangeHigh;
332 u8 antennaGainCh[AR5416_MAX_CHAINS];
333 u8 switchSettling;
334 u8 txRxAttenCh[AR5416_MAX_CHAINS];
335 u8 rxTxMarginCh[AR5416_MAX_CHAINS];
336 u8 adcDesiredSize;
337 u8 pgaDesiredSize;
338 u8 xlnaGainCh[AR5416_MAX_CHAINS];
339 u8 txEndToXpaOff;
340 u8 txEndToRxOn;
341 u8 txFrameToXpaOn;
342 u8 thresh62;
343 u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
344 u8 xpdGain;
345 u8 xpd;
346 u8 iqCalICh[AR5416_MAX_CHAINS];
347 u8 iqCalQCh[AR5416_MAX_CHAINS];
348 u8 pdGainOverlap;
349 u8 ob;
350 u8 db;
351 u8 xpaBiasLvl;
352 u8 pwrDecreaseFor2Chain;
353 u8 pwrDecreaseFor3Chain;
354 u8 txFrameToDataStart;
355 u8 txFrameToPaOn;
356 u8 ht40PowerIncForPdadc;
357 u8 bswAtten[AR5416_MAX_CHAINS];
358 u8 bswMargin[AR5416_MAX_CHAINS];
359 u8 swSettleHt40;
360 u8 xatten2Db[AR5416_MAX_CHAINS];
361 u8 xatten2Margin[AR5416_MAX_CHAINS];
362 u8 ob_ch1;
363 u8 db_ch1;
364 u8 lna_ctl;
365 u8 miscBits;
367 u8 futureModal[6];
373 u8 pwrPdg[2][5];
374 u8 vpdPdg[2][5];
375 u8 pcdac[2][5];
376 u8 empty[2][5];
382 u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
383 u8 switchSettling;
384 u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
385 u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
386 u8 adcDesiredSize;
387 u8 pgaDesiredSize;
388 u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
389 u8 txEndToXpaOff;
390 u8 txEndToRxOn;
391 u8 txFrameToXpaOn;
392 u8 thresh62;
393 u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
394 u8 xpdGain;
395 u8 xpd;
396 u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS];
397 u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
398 u8 pdGainOverlap;
400 u8 ob_1:4, ob_0:4;
401 u8 db1_1:4, db1_0:4;
403 u8 ob_0:4, ob_1:4;
404 u8 db1_0:4, db1_1:4;
406 u8 xpaBiasLvl;
407 u8 txFrameToDataStart;
408 u8 txFrameToPaOn;
409 u8 ht40PowerIncForPdadc;
410 u8 bswAtten[AR5416_EEP4K_MAX_CHAINS];
411 u8 bswMargin[AR5416_EEP4K_MAX_CHAINS];
412 u8 swSettleHt40;
413 u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS];
414 u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
416 u8 db2_1:4, db2_0:4;
418 u8 db2_0:4, db2_1:4;
420 u8 version;
422 u8 ob_3:4, ob_2:4;
423 u8 antdiv_ctl1:4, ob_4:4;
424 u8 db1_3:4, db1_2:4;
425 u8 antdiv_ctl2:4, db1_4:4;
426 u8 db2_2:4, db2_3:4;
427 u8 reserved:4, db2_4:4;
429 u8 ob_2:4, ob_3:4;
430 u8 ob_4:4, antdiv_ctl1:4;
431 u8 db1_2:4, db1_3:4;
432 u8 db1_4:4, antdiv_ctl2:4;
433 u8 db2_2:4, db2_3:4;
434 u8 db2_4:4, reserved:4;
436 u8 tx_diversity;
437 u8 flc_pwr_thresh;
438 u8 bb_scale_smrt_antenna;
440 u8 futureModal[1];
448 u8 opCapFlags;
449 u8 eepMisc;
451 u8 macAddr[6];
452 u8 rxMask;
453 u8 txMask;
458 u8 deviceType;
459 u8 openLoopPwrCntl;
463 u8 futureBase[29];
470 u8 switchSettling;
471 u8 txRxAttenCh[AR9287_MAX_CHAINS];
472 u8 rxTxMarginCh[AR9287_MAX_CHAINS];
474 u8 txEndToXpaOff;
475 u8 txEndToRxOn;
476 u8 txFrameToXpaOn;
477 u8 thresh62;
479 u8 xpdGain;
480 u8 xpd;
483 u8 pdGainOverlap;
484 u8 xpaBiasLvl;
485 u8 txFrameToDataStart;
486 u8 txFrameToPaOn;
487 u8 ht40PowerIncForPdadc;
488 u8 bswAtten[AR9287_MAX_CHAINS];
489 u8 bswMargin[AR9287_MAX_CHAINS];
490 u8 swSettleHt40;
491 u8 version;
492 u8 db1;
493 u8 db2;
494 u8 ob_cck;
495 u8 ob_psk;
496 u8 ob_qam;
497 u8 ob_pal_off;
498 u8 futureModal[30];
503 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
504 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
508 u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
509 u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
513 u8 bChannel;
514 u8 tPow2x[4];
518 u8 bChannel;
519 u8 tPow2x[8];
523 u8 bChannel;
524 u8 ctl;
528 u8 pwrPdg[2][5];
529 u8 vpdPdg[2][5];
530 u8 pcdac[2][5];
531 u8 empty[2][5];
535 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
536 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
561 u8 custData[64];
563 u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
564 u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
583 u8 ctlIndex[AR5416_NUM_CTLS];
585 u8 padding;
590 u8 custData[20];
592 u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
603 u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
605 u8 padding;
610 u8 custData[AR9287_DATA_SZ];
612 u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS];
623 u8 ctlIndex[AR9287_NUM_CTLS];
625 u8 padding;
641 u8 isMultidomain;
642 u8 iso[3];
649 u32 (*dump_eeprom)(struct ath_hw *hw, bool dump_base_hdr, u8 *buf,
656 u16 cfgCtl, u8 twiceAntennaReduction,
657 u8 powerLimit, bool test);
667 bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
672 void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
673 u8 *pVpdList, u16 numIntercepts,
674 u8 *pRetVpdList);
695 u8 *bChans, u16 availPiers,
697 u16 *pPdGainBoundaries, u8 *pPDADCValues,