Lines Matching refs:iowrite8
469 #define BYTE_REG_BITS_ON(x, p) do { iowrite8((ioread8((p))|(x)), (p)); } while (0)
477 #define BYTE_REG_BITS_OFF(x, p) do { iowrite8(ioread8((p)) & (~(x)), (p)); } while (0)
481 #define BYTE_REG_BITS_SET(x, m, p) do { iowrite8((ioread8((p)) & (~(m)))|(x), (p)); } while (0)
551 iowrite8(mask >> 16, ioaddr + IntrStatus2); in rhine_ack_events()
568 iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW); in rhine_power_init()
571 iowrite8(0x80, ioaddr + WOLcgClr); in rhine_power_init()
574 iowrite8(0xFF, ioaddr + WOLcrClr); in rhine_power_init()
577 iowrite8(0x03, ioaddr + WOLcrClr1); in rhine_power_init()
585 iowrite8(0xFF, ioaddr + PwrcsrClr); in rhine_power_init()
587 iowrite8(0x03, ioaddr + PwrcsrClr1); in rhine_power_init()
622 iowrite8(Cmd1Reset, ioaddr + ChipCmd1); in rhine_chip_reset()
630 iowrite8(0x40, ioaddr + MiscCmd); in rhine_chip_reset()
685 iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA); in rhine_reload_eeprom()
1242 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex, in rhine_check_media()
1245 iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex, in rhine_check_media()
1281 iowrite8(CAMC_CAMEN, ioaddr + CamCon); in rhine_set_cam()
1287 iowrite8((u8) idx, ioaddr + CamAddr); in rhine_set_cam()
1290 iowrite8(*addr, ioaddr + MulticastFilter0 + i); in rhine_set_cam()
1294 iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon); in rhine_set_cam()
1297 iowrite8(0, ioaddr + CamCon); in rhine_set_cam()
1310 iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon); in rhine_set_vlan_cam()
1316 iowrite8((u8) idx, ioaddr + CamAddr); in rhine_set_vlan_cam()
1322 iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon); in rhine_set_vlan_cam()
1325 iowrite8(0, ioaddr + CamCon); in rhine_set_vlan_cam()
1337 iowrite8(CAMC_CAMEN, ioaddr + CamCon); in rhine_set_cam_mask()
1344 iowrite8(0, ioaddr + CamCon); in rhine_set_cam_mask()
1356 iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon); in rhine_set_vlan_cam_mask()
1363 iowrite8(0, ioaddr + CamCon); in rhine_set_vlan_cam_mask()
1439 iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i); in init_registers()
1444 iowrite8(0x20, ioaddr + TxConfig); in init_registers()
1470 iowrite8(0, ioaddr + MIICmd); in rhine_enable_linkmon()
1471 iowrite8(MII_BMSR, ioaddr + MIIRegAddr); in rhine_enable_linkmon()
1472 iowrite8(0x80, ioaddr + MIICmd); in rhine_enable_linkmon()
1476 iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr); in rhine_enable_linkmon()
1484 iowrite8(0, ioaddr + MIICmd); in rhine_disable_linkmon()
1487 iowrite8(0x01, ioaddr + MIIRegAddr); // MII_BMSR in rhine_disable_linkmon()
1493 iowrite8(0x80, ioaddr + MIICmd); in rhine_disable_linkmon()
1498 iowrite8(0, ioaddr + MIICmd); in rhine_disable_linkmon()
1515 iowrite8(phy_id, ioaddr + MIIPhyAddr); in mdio_read()
1516 iowrite8(regnum, ioaddr + MIIRegAddr); in mdio_read()
1517 iowrite8(0x40, ioaddr + MIICmd); /* Trigger read */ in mdio_read()
1533 iowrite8(phy_id, ioaddr + MIIPhyAddr); in mdio_write()
1534 iowrite8(regnum, ioaddr + MIIRegAddr); in mdio_write()
1536 iowrite8(0x20, ioaddr + MIICmd); /* Trigger write */ in mdio_write()
1714 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand, in rhine_start_tx()
1980 iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn, in rhine_restart_tx()
1987 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand, in rhine_restart_tx()
2221 iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig); in rhine_close()
2265 iowrite8(0x04, ioaddr + WOLcgClr); in rhine_shutdown()
2270 iowrite8(WOLmagic, ioaddr + WOLcrSet); in rhine_shutdown()
2275 iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA); in rhine_shutdown()
2279 iowrite8(WOLbmcast, ioaddr + WOLcgSet); in rhine_shutdown()
2282 iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet); in rhine_shutdown()
2285 iowrite8(WOLucast, ioaddr + WOLcrSet); in rhine_shutdown()
2289 iowrite8(0x01, ioaddr + PwcfgSet); in rhine_shutdown()
2290 iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW); in rhine_shutdown()
2296 iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW); in rhine_shutdown()