34 vxge_hw_vpath_set_zero_rx_frm_len(struct vxge_hw_vpath_reg __iomem *vp_reg)  in vxge_hw_vpath_set_zero_rx_frm_len()  argument
38 	val64 = readq(&vp_reg->rxmac_vcfg0);  in vxge_hw_vpath_set_zero_rx_frm_len()
40 	writeq(val64, &vp_reg->rxmac_vcfg0);  in vxge_hw_vpath_set_zero_rx_frm_len()
41 	val64 = readq(&vp_reg->rxmac_vcfg0);  in vxge_hw_vpath_set_zero_rx_frm_len()
49 	struct vxge_hw_vpath_reg __iomem *vp_reg;  in vxge_hw_vpath_wait_receive_idle()  local
55 	vp_reg = vpath->vp_reg;  in vxge_hw_vpath_wait_receive_idle()
57 	vxge_hw_vpath_set_zero_rx_frm_len(vp_reg);  in vxge_hw_vpath_wait_receive_idle()
64 	val64 = readq(&vp_reg->prc_cfg6);  in vxge_hw_vpath_wait_receive_idle()
74 		rxd_count = readq(&vp_reg->prc_rxd_doorbell);  in vxge_hw_vpath_wait_receive_idle()
79 		val64 = readq(&vp_reg->frm_in_progress_cnt);  in vxge_hw_vpath_wait_receive_idle()
162 	struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;  in vxge_hw_vpath_fw_api()  local
173 	writeq(*data0, &vp_reg->rts_access_steer_data0);  in vxge_hw_vpath_fw_api()
174 	writeq(*data1, &vp_reg->rts_access_steer_data1);  in vxge_hw_vpath_fw_api()
184 					   &vp_reg->rts_access_steer_ctrl,  in vxge_hw_vpath_fw_api()
200 					&vp_reg->rts_access_steer_ctrl,  in vxge_hw_vpath_fw_api()
208 	val64 = readq(&vp_reg->rts_access_steer_ctrl);  in vxge_hw_vpath_fw_api()
210 		*data0 = readq(&vp_reg->rts_access_steer_data0);  in vxge_hw_vpath_fw_api()
211 		*data1 = readq(&vp_reg->rts_access_steer_data1);  in vxge_hw_vpath_fw_api()
742 		hldev->virtual_paths[i].vp_reg = hldev->vpath_reg[i];  in __vxge_hw_device_host_info_get()
1056 		vpath.vp_reg = bar0 + val64;  in vxge_hw_device_hw_info_get()
1079 		vpath.vp_reg = bar0 + val64;  in vxge_hw_device_hw_info_get()
1419 	struct vxge_hw_vpath_reg __iomem *vp_reg;  in __vxge_hw_vpath_stats_access()  local
1426 	vp_reg = vpath->vp_reg;  in __vxge_hw_vpath_stats_access()
1433 				&vp_reg->xmac_stats_access_cmd,  in __vxge_hw_vpath_stats_access()
1437 		*stat = readq(&vp_reg->xmac_stats_access_data);  in __vxge_hw_vpath_stats_access()
1517 	struct vxge_hw_vpath_reg __iomem *vp_reg;  in __vxge_hw_vpath_stats_get()  local
1523 	vp_reg = vpath->vp_reg;  in __vxge_hw_vpath_stats_get()
1525 	val64 = readq(&vp_reg->vpath_debug_stats0);  in __vxge_hw_vpath_stats_get()
1529 	val64 = readq(&vp_reg->vpath_debug_stats1);  in __vxge_hw_vpath_stats_get()
1533 	val64 = readq(&vp_reg->vpath_debug_stats2);  in __vxge_hw_vpath_stats_get()
1537 	val64 = readq(&vp_reg->vpath_debug_stats3);  in __vxge_hw_vpath_stats_get()
1541 	val64 = readq(&vp_reg->vpath_debug_stats4);  in __vxge_hw_vpath_stats_get()
1545 	val64 = readq(&vp_reg->vpath_debug_stats5);  in __vxge_hw_vpath_stats_get()
1549 	val64 = readq(&vp_reg->vpath_debug_stats6);  in __vxge_hw_vpath_stats_get()
1553 	val64 = readq(&vp_reg->vpath_genstats_count01);  in __vxge_hw_vpath_stats_get()
1558 	val64 = readq(&vp_reg->vpath_genstats_count01);  in __vxge_hw_vpath_stats_get()
1563 	val64 = readq(&vp_reg->vpath_genstats_count23);  in __vxge_hw_vpath_stats_get()
1568 	val64 = readq(&vp_reg->vpath_genstats_count01);  in __vxge_hw_vpath_stats_get()
1573 	val64 = readq(&vp_reg->vpath_genstats_count4);  in __vxge_hw_vpath_stats_get()
1578 	val64 = readq(&vp_reg->vpath_genstats_count5);  in __vxge_hw_vpath_stats_get()
1609 	val64 = readq(&vp_reg->rx_multi_cast_stats);  in __vxge_hw_vpath_stats_get()
1613 	val64 = readq(&vp_reg->rx_frm_transferred);  in __vxge_hw_vpath_stats_get()
1617 	val64 = readq(&vp_reg->rxd_returned);  in __vxge_hw_vpath_stats_get()
1621 	val64 = readq(&vp_reg->dbg_stats_rx_mpa);  in __vxge_hw_vpath_stats_get()
1629 	val64 = readq(&vp_reg->dbg_stats_rx_fau);  in __vxge_hw_vpath_stats_get()
1637 	val64 = readq(&vp_reg->tx_vp_reset_discarded_frms);  in __vxge_hw_vpath_stats_get()
2847 	ring->vp_reg = vp->vpath->vp_reg;  in __vxge_hw_ring_create()
3492 	fifo->vp_reg = vpath->vp_reg;  in __vxge_hw_fifo_create()
3587 	struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;  in __vxge_hw_vpath_pci_read()  local
3594 	writeq(val64, &vp_reg->pci_config_access_cfg1);  in __vxge_hw_vpath_pci_read()
3597 			&vp_reg->pci_config_access_cfg2);  in __vxge_hw_vpath_pci_read()
3601 			&vp_reg->pci_config_access_cfg2,  in __vxge_hw_vpath_pci_read()
3607 	val64 = readq(&vp_reg->pci_config_access_status);  in __vxge_hw_vpath_pci_read()
3961 	rxd_new_count = readl(&ring->vp_reg->prc_rxd_doorbell);  in vxge_hw_vpath_check_leak()
3962 	rxd_spat = readq(&ring->vp_reg->prc_cfg6);  in vxge_hw_vpath_check_leak()
4087 	struct vxge_hw_vpath_reg __iomem *vp_reg;  in __vxge_hw_vpath_prc_configure()  local
4090 	vp_reg = vpath->vp_reg;  in __vxge_hw_vpath_prc_configure()
4096 	val64 = readq(&vp_reg->prc_cfg1);  in __vxge_hw_vpath_prc_configure()
4098 	writeq(val64, &vp_reg->prc_cfg1);  in __vxge_hw_vpath_prc_configure()
4100 	val64 = readq(&vpath->vp_reg->prc_cfg6);  in __vxge_hw_vpath_prc_configure()
4102 	writeq(val64, &vpath->vp_reg->prc_cfg6);  in __vxge_hw_vpath_prc_configure()
4104 	val64 = readq(&vp_reg->prc_cfg7);  in __vxge_hw_vpath_prc_configure()
4127 	writeq(val64, &vp_reg->prc_cfg7);  in __vxge_hw_vpath_prc_configure()
4131 					vpath->ringh) >> 3), &vp_reg->prc_cfg5);  in __vxge_hw_vpath_prc_configure()
4133 	val64 = readq(&vp_reg->prc_cfg4);  in __vxge_hw_vpath_prc_configure()
4145 	writeq(val64, &vp_reg->prc_cfg4);  in __vxge_hw_vpath_prc_configure()
4160 	struct vxge_hw_vpath_reg __iomem *vp_reg;  in __vxge_hw_vpath_kdfc_configure()  local
4163 	vp_reg = vpath->vp_reg;  in __vxge_hw_vpath_kdfc_configure()
4164 	status = __vxge_hw_kdfc_swapper_set(hldev->legacy_reg, vp_reg);  in __vxge_hw_vpath_kdfc_configure()
4169 	val64 = readq(&vp_reg->kdfc_drbl_triplet_total);  in __vxge_hw_vpath_kdfc_configure()
4191 	writeq(val64, &vp_reg->kdfc_fifo_trpl_partition);  in __vxge_hw_vpath_kdfc_configure()
4194 		&vp_reg->kdfc_fifo_trpl_ctrl);  in __vxge_hw_vpath_kdfc_configure()
4196 	val64 = readq(&vp_reg->kdfc_trpl_fifo_0_ctrl);  in __vxge_hw_vpath_kdfc_configure()
4208 	writeq(val64, &vp_reg->kdfc_trpl_fifo_0_ctrl);  in __vxge_hw_vpath_kdfc_configure()
4209 	writeq((u64)0, &vp_reg->kdfc_trpl_fifo_0_wb_address);  in __vxge_hw_vpath_kdfc_configure()
4233 	struct vxge_hw_vpath_reg __iomem *vp_reg;  in __vxge_hw_vpath_mac_configure()  local
4236 	vp_reg = vpath->vp_reg;  in __vxge_hw_vpath_mac_configure()
4240 			vpath->vsport_number), &vp_reg->xmac_vsport_choice);  in __vxge_hw_vpath_mac_configure()
4244 		val64 = readq(&vp_reg->xmac_rpa_vcfg);  in __vxge_hw_vpath_mac_configure()
4254 		writeq(val64, &vp_reg->xmac_rpa_vcfg);  in __vxge_hw_vpath_mac_configure()
4255 		val64 = readq(&vp_reg->rxmac_vcfg0);  in __vxge_hw_vpath_mac_configure()
4270 		writeq(val64, &vp_reg->rxmac_vcfg0);  in __vxge_hw_vpath_mac_configure()
4272 		val64 = readq(&vp_reg->rxmac_vcfg1);  in __vxge_hw_vpath_mac_configure()
4284 		writeq(val64, &vp_reg->rxmac_vcfg1);  in __vxge_hw_vpath_mac_configure()
4300 	struct vxge_hw_vpath_reg __iomem *vp_reg;  in __vxge_hw_vpath_tim_configure()  local
4304 	vp_reg = vpath->vp_reg;  in __vxge_hw_vpath_tim_configure()
4307 	writeq(0, &vp_reg->tim_dest_addr);  in __vxge_hw_vpath_tim_configure()
4308 	writeq(0, &vp_reg->tim_vpath_map);  in __vxge_hw_vpath_tim_configure()
4309 	writeq(0, &vp_reg->tim_bitmap);  in __vxge_hw_vpath_tim_configure()
4310 	writeq(0, &vp_reg->tim_remap);  in __vxge_hw_vpath_tim_configure()
4315 			VXGE_HW_VPATH_INTR_RX), &vp_reg->tim_ring_assn);  in __vxge_hw_vpath_tim_configure()
4317 	val64 = readq(&vp_reg->tim_pci_cfg);  in __vxge_hw_vpath_tim_configure()
4319 	writeq(val64, &vp_reg->tim_pci_cfg);  in __vxge_hw_vpath_tim_configure()
4323 		val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);  in __vxge_hw_vpath_tim_configure()
4366 		writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);  in __vxge_hw_vpath_tim_configure()
4369 		val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);  in __vxge_hw_vpath_tim_configure()
4395 		writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);  in __vxge_hw_vpath_tim_configure()
4396 		val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);  in __vxge_hw_vpath_tim_configure()
4424 		writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);  in __vxge_hw_vpath_tim_configure()
4430 		val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);  in __vxge_hw_vpath_tim_configure()
4473 		writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);  in __vxge_hw_vpath_tim_configure()
4476 		val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);  in __vxge_hw_vpath_tim_configure()
4502 		writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);  in __vxge_hw_vpath_tim_configure()
4503 		val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);  in __vxge_hw_vpath_tim_configure()
4531 		writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);  in __vxge_hw_vpath_tim_configure()
4536 	writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_EINTA]);  in __vxge_hw_vpath_tim_configure()
4537 	writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_EINTA]);  in __vxge_hw_vpath_tim_configure()
4538 	writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_EINTA]);  in __vxge_hw_vpath_tim_configure()
4539 	writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_BMAP]);  in __vxge_hw_vpath_tim_configure()
4540 	writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_BMAP]);  in __vxge_hw_vpath_tim_configure()
4541 	writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_BMAP]);  in __vxge_hw_vpath_tim_configure()
4546 	writeq(val64, &vp_reg->tim_wrkld_clc);  in __vxge_hw_vpath_tim_configure()
4563 	struct vxge_hw_vpath_reg __iomem *vp_reg;  in __vxge_hw_vpath_initialize()  local
4571 	vp_reg = vpath->vp_reg;  in __vxge_hw_vpath_initialize()
4573 	status =  __vxge_hw_vpath_swapper_set(vpath->vp_reg);  in __vxge_hw_vpath_initialize()
4589 	val64 = readq(&vp_reg->rtdma_rd_optimization_ctrl);  in __vxge_hw_vpath_initialize()
4609 	writeq(val64, &vp_reg->rtdma_rd_optimization_ctrl);  in __vxge_hw_vpath_initialize()
4681 	vpath->vp_reg = hldev->vpath_reg[vp_id];  in __vxge_hw_vp_initialize()
4735 	val64 = readq(&vpath->vp_reg->rxmac_vcfg0);  in vxge_hw_vpath_mtu_set()
4740 	writeq(val64, &vpath->vp_reg->rxmac_vcfg0);  in vxge_hw_vpath_mtu_set()
4878 	writeq(vpath->stats_block->dma_addr, &vpath->vp_reg->stats_cfg);  in vxge_hw_vpath_open()
4926 		new_count = readq(&vpath->vp_reg->rxdmem_size);  in vxge_hw_vpath_rx_doorbell_init()
4934 		&vpath->vp_reg->prc_rxd_doorbell);  in vxge_hw_vpath_rx_doorbell_init()
4935 	readl(&vpath->vp_reg->prc_rxd_doorbell);  in vxge_hw_vpath_rx_doorbell_init()
4938 	val64 = readq(&vpath->vp_reg->prc_cfg6);  in vxge_hw_vpath_rx_doorbell_init()
5096 		&vpath->vp_reg->stats_cfg);  in vxge_hw_vpath_recover_from_reset()