276 	REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);  in bnx2_reg_rd_ind()
286 	REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);  in bnx2_reg_wr_ind()
287 	REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);  in bnx2_reg_wr_ind()
311 		REG_WR(bp, BNX2_CTX_CTX_DATA, val);  in bnx2_ctx_wr()
312 		REG_WR(bp, BNX2_CTX_CTX_CTRL,  in bnx2_ctx_wr()
321 		REG_WR(bp, BNX2_CTX_DATA_ADR, offset);  in bnx2_ctx_wr()
322 		REG_WR(bp, BNX2_CTX_DATA, val);  in bnx2_ctx_wr()
499 		REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_read_phy()
508 	REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);  in bnx2_read_phy()
537 		REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_read_phy()
556 		REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_write_phy()
565 	REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);  in bnx2_write_phy()
586 		REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_write_phy()
603 		REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_disable_int()
618 		REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_enable_int()
623 		REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_enable_int()
627 	REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);  in bnx2_enable_int()
1297 	REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);  in bnx2_set_mac_link()
1300 		REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);  in bnx2_set_mac_link()
1336 	REG_WR(bp, BNX2_EMAC_MODE, val);  in bnx2_set_mac_link()
1343 	REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);  in bnx2_set_mac_link()
1351 	REG_WR(bp, BNX2_EMAC_TX_MODE, val);  in bnx2_set_mac_link()
1354 	REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);  in bnx2_set_mac_link()
1945 	REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);  in bnx2_send_heart_beat()
1946 	REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);  in bnx2_send_heart_beat()
2268         	REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);  in bnx2_init_5706s_phy()
2367         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);  in bnx2_init_phy()
2404 	REG_WR(bp, BNX2_EMAC_MODE, mac_mode);  in bnx2_set_mac_loopback()
2436 	REG_WR(bp, BNX2_EMAC_MODE, mac_mode);  in bnx2_set_phy_loopback()
2537 	REG_WR(bp, BNX2_CTX_COMMAND, val);  in bnx2_init_5709_context()
2555 		REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,  in bnx2_init_5709_context()
2558 		REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,  in bnx2_init_5709_context()
2560 		REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |  in bnx2_init_5709_context()
2610 			REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);  in bnx2_init_context()
2611 			REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);  in bnx2_init_context()
2631 	REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,  in bnx2_alloc_bad_rbuf()
2676 	REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);  in bnx2_set_mac_addr()
2681 	REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);  in bnx2_set_mac_addr()
2768 			REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);  in bnx2_phy_event_is_set()
2770 			REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);  in bnx2_phy_event_is_set()
3257 	REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);  in bnx2_rx_int()
3275 	REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_msi()
3323 	REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_interrupt()
3391 			REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &  in bnx2_chk_missed_msi()
3393 			REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);  in bnx2_chk_missed_msi()
3432 		REG_WR(bp, BNX2_HC_COMMAND,  in bnx2_poll_link()
3471 			REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_poll_msix()
3509 				REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_poll()
3514 			REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_poll()
3519 			REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_poll()
3559 			REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),  in bnx2_set_rx_mode()
3582 			REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),  in bnx2_set_rx_mode()
3608 		REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);  in bnx2_set_rx_mode()
3611 	REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);  in bnx2_set_rx_mode()
3612 	REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);  in bnx2_set_rx_mode()
3613 	REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);  in bnx2_set_rx_mode()
3754 		REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));  in load_rv2p_fw()
3756 		REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));  in load_rv2p_fw()
3760 		REG_WR(bp, addr, val);  in load_rv2p_fw()
3770 			REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);  in load_rv2p_fw()
3773 			REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);  in load_rv2p_fw()
3776 			REG_WR(bp, addr, val);  in load_rv2p_fw()
3782 		REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);  in load_rv2p_fw()
3785 		REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);  in load_rv2p_fw()
3925 		REG_WR(bp, BNX2_EMAC_MODE, val);  in bnx2_set_power_state()
3929 		REG_WR(bp, BNX2_RPM_CONFIG, val);  in bnx2_set_power_state()
3976 			REG_WR(bp, BNX2_EMAC_MODE, val);  in bnx2_set_power_state()
3980 				REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),  in bnx2_set_power_state()
3983 			REG_WR(bp, BNX2_EMAC_RX_MODE,  in bnx2_set_power_state()
3988 			REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);  in bnx2_set_power_state()
3989 			REG_WR(bp, BNX2_RPM_SORT_USER0, val);  in bnx2_set_power_state()
3990 			REG_WR(bp, BNX2_RPM_SORT_USER0, val |  in bnx2_set_power_state()
3994 			REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,  in bnx2_set_power_state()
4001 			REG_WR(bp, BNX2_RPM_CONFIG, val);  in bnx2_set_power_state()
4048 	REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);  in bnx2_acquire_nvram_lock()
4070 	REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);  in bnx2_release_nvram_lock()
4093 	REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);  in bnx2_enable_nvram_write()
4098 		REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_enable_nvram_write()
4099 		REG_WR(bp, BNX2_NVM_COMMAND,  in bnx2_enable_nvram_write()
4122 	REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);  in bnx2_disable_nvram_write()
4133 	REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,  in bnx2_enable_nvram_access()
4144 	REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,  in bnx2_disable_nvram_access()
4164 	REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_nvram_erase_page()
4167 	REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);  in bnx2_nvram_erase_page()
4170 	REG_WR(bp, BNX2_NVM_COMMAND, cmd);  in bnx2_nvram_erase_page()
4206 	REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_nvram_read_dword()
4209 	REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);  in bnx2_nvram_read_dword()
4212 	REG_WR(bp, BNX2_NVM_COMMAND, cmd);  in bnx2_nvram_read_dword()
4252 	REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_nvram_write_dword()
4257 	REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));  in bnx2_nvram_write_dword()
4260 	REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);  in bnx2_nvram_write_dword()
4263 	REG_WR(bp, BNX2_NVM_COMMAND, cmd);  in bnx2_nvram_write_dword()
4330 				REG_WR(bp, BNX2_NVM_CFG1, flash->config1);  in bnx2_init_nvram()
4331 				REG_WR(bp, BNX2_NVM_CFG2, flash->config2);  in bnx2_init_nvram()
4332 				REG_WR(bp, BNX2_NVM_CFG3, flash->config3);  in bnx2_init_nvram()
4333 				REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);  in bnx2_init_nvram()
4694 	REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);  in bnx2_setup_msix_tbl()
4696 	REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);  in bnx2_setup_msix_tbl()
4697 	REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);  in bnx2_setup_msix_tbl()
4711 		REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,  in bnx2_reset_chip()
4721 		REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);  in bnx2_reset_chip()
4745 		REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);  in bnx2_reset_chip()
4752 		REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);  in bnx2_reset_chip()
4760 		REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);  in bnx2_reset_chip()
4809 		REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);  in bnx2_reset_chip()
4818 		REG_WR(bp, BNX2_MISC_ECO_HW_CTL,  in bnx2_reset_chip()
4832 	REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);  in bnx2_init_chip()
4852 	REG_WR(bp, BNX2_DMA_CONFIG, val);  in bnx2_init_chip()
4857 		REG_WR(bp, BNX2_TDMA_CONFIG, val);  in bnx2_init_chip()
4869 	REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,  in bnx2_init_chip()
4899 	REG_WR(bp, BNX2_MQ_CONFIG, val);  in bnx2_init_chip()
4902 	REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);  in bnx2_init_chip()
4903 	REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);  in bnx2_init_chip()
4906 	REG_WR(bp, BNX2_RV2P_CONFIG, val);  in bnx2_init_chip()
4912 	REG_WR(bp, BNX2_TBDR_CONFIG, val);  in bnx2_init_chip()
4920 	REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);  in bnx2_init_chip()
4927 	REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);  in bnx2_init_chip()
4945 	REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);  in bnx2_init_chip()
4947 	REG_WR(bp, BNX2_HC_STATUS_ADDR_L,  in bnx2_init_chip()
4949 	REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);  in bnx2_init_chip()
4951 	REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,  in bnx2_init_chip()
4953 	REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,  in bnx2_init_chip()
4956 	REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,  in bnx2_init_chip()
4959 	REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,  in bnx2_init_chip()
4962 	REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,  in bnx2_init_chip()
4965 	REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);  in bnx2_init_chip()
4967 	REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);  in bnx2_init_chip()
4969 	REG_WR(bp, BNX2_HC_COM_TICKS,  in bnx2_init_chip()
4972 	REG_WR(bp, BNX2_HC_CMD_TICKS,  in bnx2_init_chip()
4976 		REG_WR(bp, BNX2_HC_STATS_TICKS, 0);  in bnx2_init_chip()
4978 		REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);  in bnx2_init_chip()
4979 	REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */  in bnx2_init_chip()
4989 		REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,  in bnx2_init_chip()
4998 	REG_WR(bp, BNX2_HC_CONFIG, val);  in bnx2_init_chip()
5009 		REG_WR(bp, base,  in bnx2_init_chip()
5014 		REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,  in bnx2_init_chip()
5018 		REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,  in bnx2_init_chip()
5021 		REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,  in bnx2_init_chip()
5025 		REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,  in bnx2_init_chip()
5030 	REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);  in bnx2_init_chip()
5032 	REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);  in bnx2_init_chip()
5040 		REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);  in bnx2_init_chip()
5045 	REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);  in bnx2_init_chip()
5187 		REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);  in bnx2_init_rx_ring()
5207 			REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);  in bnx2_init_rx_ring()
5247 	REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);  in bnx2_init_rx_ring()
5258 	REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);  in bnx2_init_all_rings()
5263 		REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |  in bnx2_init_all_rings()
5266 	REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);  in bnx2_init_all_rings()
5280 				REG_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32);  in bnx2_init_all_rings()
5281 				REG_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) |  in bnx2_init_all_rings()
5292 		REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);  in bnx2_init_all_rings()
5782 	REG_WR(bp, BNX2_HC_COMMAND,  in bnx2_run_loopback()
5804 	REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);  in bnx2_run_loopback()
5808 	REG_WR(bp, BNX2_HC_COMMAND,  in bnx2_run_loopback()
5963 	REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);  in bnx2_test_intr()
6130 		REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |  in bnx2_timer()
6203 	REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);  in bnx2_enable_msix()
6204 	REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);  in bnx2_enable_msix()
6205 	REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);  in bnx2_enable_msix()
6577 	REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);  in bnx2_start_xmit()
7577 		REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);  in bnx2_set_phys_id()
7581 		REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |  in bnx2_set_phys_id()
7590 		REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);  in bnx2_set_phys_id()
7594 		REG_WR(bp, BNX2_EMAC_LED, 0);  in bnx2_set_phys_id()
7595 		REG_WR(bp, BNX2_MISC_CFG, bp->leds_save);  in bnx2_set_phys_id()
8058 	REG_WR(bp, BNX2_PCICFG_MISC_CONFIG,  in bnx2_init_board()
8127 		REG_WR(bp, PCI_COMMAND, reg);  in bnx2_init_board()