468 	*R_NETWORK_MGM_CTRL = IO_STATE(R_NETWORK_MGM_CTRL, mdoe, enable);  in e100_open()
471 		IO_STATE(R_IRQ_MASK0_CLR, overrun, clr) |  in e100_open()
472 		IO_STATE(R_IRQ_MASK0_CLR, underrun, clr) |  in e100_open()
473 		IO_STATE(R_IRQ_MASK0_CLR, excessive_col, clr);  in e100_open()
477 		IO_STATE(R_IRQ_MASK2_CLR, dma0_descr, clr) |  in e100_open()
478 		IO_STATE(R_IRQ_MASK2_CLR, dma0_eop, clr) |  in e100_open()
479 		IO_STATE(R_IRQ_MASK2_CLR, dma1_descr, clr) |  in e100_open()
480 		IO_STATE(R_IRQ_MASK2_CLR, dma1_eop, clr);  in e100_open()
553 		IO_STATE(R_NETWORK_GEN_CONFIG, phy,    mii_clk) |  in e100_open()
554 		IO_STATE(R_NETWORK_GEN_CONFIG, enable, on);  in e100_open()
570 		IO_STATE(R_IRQ_MASK2_SET, dma0_eop, set) |  in e100_open()
571 		IO_STATE(R_IRQ_MASK2_SET, dma1_eop, set);  in e100_open()
574 		IO_STATE(R_IRQ_MASK0_SET, overrun,       set) |  in e100_open()
575 		IO_STATE(R_IRQ_MASK0_SET, underrun,      set) |  in e100_open()
576 		IO_STATE(R_IRQ_MASK0_SET, excessive_col, set);  in e100_open()
580 	*R_DMA_CH0_CLR_INTR = IO_STATE(R_DMA_CH0_CLR_INTR, clr_eop, do);  in e100_open()
581 	*R_DMA_CH1_CLR_INTR = IO_STATE(R_DMA_CH1_CLR_INTR, clr_eop, do);  in e100_open()
591 	*R_DMA_CH1_CMD = IO_STATE(R_DMA_CH1_CMD, cmd, start);  in e100_open()
1000 		IO_STATE(R_NETWORK_MGM_CTRL, mdoe, enable) |  in e100_send_mdio_bit()
1004 		IO_STATE(R_NETWORK_MGM_CTRL, mdoe, enable) |  in e100_send_mdio_bit()
1145 	if (irqbits & IO_STATE(R_IRQ_MASK2_RD, dma1_eop, active)) {  in e100rxtx_interrupt()
1148 		*R_DMA_CH1_CLR_INTR = IO_STATE(R_DMA_CH1_CLR_INTR, clr_eop, do);  in e100rxtx_interrupt()
1160 			*R_DMA_CH1_CMD = IO_STATE(R_DMA_CH1_CMD, cmd, restart);  in e100rxtx_interrupt()
1163 				IO_STATE(R_DMA_CH1_CLR_INTR, clr_eop, do) |  in e100rxtx_interrupt()
1164 				IO_STATE(R_DMA_CH1_CLR_INTR, clr_descr, do);  in e100rxtx_interrupt()
1186 	if (irqbits & IO_STATE(R_IRQ_MASK2_RD, dma0_eop, active)) {  in e100rxtx_interrupt()
1188 		*R_DMA_CH0_CLR_INTR = IO_STATE(R_DMA_CH0_CLR_INTR, clr_eop, do);  in e100rxtx_interrupt()
1201 	if (irqbits & IO_STATE(R_IRQ_MASK0_RD, underrun, active)) {  in e100nw_interrupt()
1210 	if (irqbits & IO_STATE(R_IRQ_MASK0_RD, overrun, active)) {  in e100nw_interrupt()
1215 	if (irqbits & IO_STATE(R_IRQ_MASK0_RD, excessive_col, active)) {  in e100nw_interrupt()
1338 		IO_STATE(R_IRQ_MASK0_CLR, overrun, clr) |  in e100_close()
1339 		IO_STATE(R_IRQ_MASK0_CLR, underrun, clr) |  in e100_close()
1340 		IO_STATE(R_IRQ_MASK0_CLR, excessive_col, clr);  in e100_close()
1343 		IO_STATE(R_IRQ_MASK2_CLR, dma0_descr, clr) |  in e100_close()
1344 		IO_STATE(R_IRQ_MASK2_CLR, dma0_eop, clr) |  in e100_close()
1345 		IO_STATE(R_IRQ_MASK2_CLR, dma1_descr, clr) |  in e100_close()
1346 		IO_STATE(R_IRQ_MASK2_CLR, dma1_eop, clr);  in e100_close()
1665 	*R_DMA_CH0_CMD = IO_STATE(R_DMA_CH0_CMD, cmd, restart);  in e100_hardware_send_packet()