34 #define NDCR		(0x00) /* Control register */  macro
309 	nand_writel(info, NDCR, 0);  in pxa3xx_nand_start()
311 	nand_writel(info, NDCR, ndcr);  in pxa3xx_nand_start()
320 	ndcr = nand_readl(info, NDCR);  in pxa3xx_nand_stop()
322 		ndcr = nand_readl(info, NDCR);  in pxa3xx_nand_stop()
328 		nand_writel(info, NDCR, ndcr);  in pxa3xx_nand_stop()
338 	ndcr = nand_readl(info, NDCR);  in enable_int()
339 	nand_writel(info, NDCR, ndcr & ~int_mask);  in enable_int()
346 	ndcr = nand_readl(info, NDCR);  in disable_int()
347 	nand_writel(info, NDCR, ndcr | int_mask);  in disable_int()
857 	uint32_t ndcr = nand_readl(info, NDCR);  in pxa3xx_nand_detect_config()