381 		pc = readl(FSMC_NAND_REG(regs, bank, PC));  in fsmc_cmd_ctrl()
386 		writel(pc, FSMC_NAND_REG(regs, bank, PC));  in fsmc_cmd_ctrl()
429 		writel(value | FSMC_DEVWID_16, FSMC_NAND_REG(regs, bank, PC));  in fsmc_nand_setup()
431 		writel(value | FSMC_DEVWID_8, FSMC_NAND_REG(regs, bank, PC));  in fsmc_nand_setup()
433 	writel(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,  in fsmc_nand_setup()
434 			FSMC_NAND_REG(regs, bank, PC));  in fsmc_nand_setup()
435 	writel(thiz | thold | twait | tset, FSMC_NAND_REG(regs, bank, COMM));  in fsmc_nand_setup()
436 	writel(thiz | thold | twait | tset, FSMC_NAND_REG(regs, bank, ATTRIB));  in fsmc_nand_setup()
449 	writel(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,  in fsmc_enable_hwecc()
450 			FSMC_NAND_REG(regs, bank, PC));  in fsmc_enable_hwecc()
451 	writel(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,  in fsmc_enable_hwecc()
452 			FSMC_NAND_REG(regs, bank, PC));  in fsmc_enable_hwecc()
453 	writel(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,  in fsmc_enable_hwecc()
454 			FSMC_NAND_REG(regs, bank, PC));  in fsmc_enable_hwecc()
473 		if (readl(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)  in fsmc_read_hwecc_ecc4()
484 	ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC1));  in fsmc_read_hwecc_ecc4()
490 	ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC2));  in fsmc_read_hwecc_ecc4()
496 	ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC3));  in fsmc_read_hwecc_ecc4()
502 	ecc_tmp = readl(FSMC_NAND_REG(regs, bank, STS));  in fsmc_read_hwecc_ecc4()
522 	ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC1));  in fsmc_read_hwecc_ecc1()
782 	num_err = (readl(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;  in fsmc_bch8_correct_data()
825 	ecc1 = readl(FSMC_NAND_REG(regs, bank, ECC1));  in fsmc_bch8_correct_data()
826 	ecc2 = readl(FSMC_NAND_REG(regs, bank, ECC2));  in fsmc_bch8_correct_data()
827 	ecc3 = readl(FSMC_NAND_REG(regs, bank, ECC3));  in fsmc_bch8_correct_data()
828 	ecc4 = readl(FSMC_NAND_REG(regs, bank, STS));  in fsmc_bch8_correct_data()