Lines Matching refs:hfcsx
64 byteout(cs->hw.hfcsx.base + 1, regnum); in Write_hfc()
65 byteout(cs->hw.hfcsx.base, val); in Write_hfc()
73 byteout(cs->hw.hfcsx.base + 1, regnum); in Read_hfc()
74 ret = bytein(cs->hw.hfcsx.base); in Read_hfc()
85 if (fifo == cs->hw.hfcsx.last_fifo) in fifo_select()
88 byteout(cs->hw.hfcsx.base + 1, HFCSX_FIF_SEL); in fifo_select()
89 byteout(cs->hw.hfcsx.base, fifo); in fifo_select()
90 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ in fifo_select()
92 byteout(cs->hw.hfcsx.base, fifo); in fifo_select()
93 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ in fifo_select()
104 byteout(cs->hw.hfcsx.base + 1, HFCSX_CIRM); in reset_fifo()
105 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.cirm | 0x80); /* reset cmd */ in reset_fifo()
107 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ in reset_fifo()
133 fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */ in write_fifo()
157 msp = ((struct hfcsx_extra *)(cs->hw.hfcsx.extra))->marker; in write_fifo()
197 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ in write_fifo()
220 fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */ in read_fifo()
302 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ in read_fifo()
314 cs->hw.hfcsx.int_m2 = 0; /* interrupt output off ! */ in release_io_hfcsx()
315 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); in release_io_hfcsx()
319 del_timer(&cs->hw.hfcsx.timer); in release_io_hfcsx()
320 release_region(cs->hw.hfcsx.base, 2); /* release IO-Block */ in release_io_hfcsx()
321 kfree(cs->hw.hfcsx.extra); in release_io_hfcsx()
322 cs->hw.hfcsx.extra = NULL; in release_io_hfcsx()
332 if (cs->hw.hfcsx.b_fifo_size) return (1); /* already determined */ in set_fifo_size()
334 if ((cs->hw.hfcsx.chip >> 4) == 9) { in set_fifo_size()
335 cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_32K; in set_fifo_size()
339 cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_8K; in set_fifo_size()
340 cs->hw.hfcsx.cirm |= 0x10; /* only 8K of ram */ in set_fifo_size()
352 cs->hw.hfcsx.int_m2 = 0; /* interrupt output off ! */ in reset_hfcsx()
353 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); in reset_hfcsx()
357 Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET | cs->hw.hfcsx.cirm); /* Reset */ in reset_hfcsx()
359 Write_hfc(cs, HFCSX_CIRM, cs->hw.hfcsx.cirm); /* Reset Off */ in reset_hfcsx()
363 cs->hw.hfcsx.last_fifo = 0xff; /* invalidate */ in reset_hfcsx()
368 cs->hw.hfcsx.trm = 0 + HFCSX_BTRANS_THRESMASK; /* no echo connect , threshold */ in reset_hfcsx()
369 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm); in reset_hfcsx()
372 cs->hw.hfcsx.sctrl_e = HFCSX_AUTO_AWAKE; in reset_hfcsx()
373 Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e); /* S/T Auto awake */ in reset_hfcsx()
374 cs->hw.hfcsx.bswapped = 0; /* no exchange */ in reset_hfcsx()
375 cs->hw.hfcsx.nt_mode = 0; /* we are in TE mode */ in reset_hfcsx()
376 cs->hw.hfcsx.ctmt = HFCSX_TIM3_125 | HFCSX_AUTO_TIMER; in reset_hfcsx()
377 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt); in reset_hfcsx()
379 cs->hw.hfcsx.int_m1 = HFCSX_INTS_DTRANS | HFCSX_INTS_DREC | in reset_hfcsx()
381 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in reset_hfcsx()
389 cs->hw.hfcsx.mst_m = HFCSX_MASTER; /* HFC Master Mode */ in reset_hfcsx()
391 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); in reset_hfcsx()
392 cs->hw.hfcsx.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */ in reset_hfcsx()
393 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); in reset_hfcsx()
394 cs->hw.hfcsx.sctrl_r = 0; in reset_hfcsx()
395 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r); in reset_hfcsx()
404 cs->hw.hfcsx.conn = 0x36; /* set data flow directions */ in reset_hfcsx()
405 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); in reset_hfcsx()
412 cs->hw.hfcsx.int_m2 = HFCSX_IRQ_ENABLE; in reset_hfcsx()
413 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); in reset_hfcsx()
423 cs->hw.hfcsx.timer.expires = jiffies + 75; in hfcsx_Timer()
488 skb = read_fifo(cs, ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ? in main_rec_hfcsx()
536 ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ? in hfcsx_fill_fifo()
601 …(!(cs->hw.hfcsx.int_m1 & (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC + HFCSX_INTS_B1TRANS + HFCSX_INTS_… in hfcsx_auxcmd()
605 cs->hw.hfcsx.sctrl |= SCTRL_MODE_NT; in hfcsx_auxcmd()
606 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); /* set NT-mode */ in hfcsx_auxcmd()
611 cs->dc.hfcsx.ph_state = 1; in hfcsx_auxcmd()
612 cs->hw.hfcsx.nt_mode = 1; in hfcsx_auxcmd()
613 cs->hw.hfcsx.nt_timer = 0; in hfcsx_auxcmd()
619 if ((cs->chanlimit > 1) || (cs->hw.hfcsx.bswapped) || in hfcsx_auxcmd()
620 (cs->hw.hfcsx.nt_mode) || (ic->arg != 12)) in hfcsx_auxcmd()
625 cs->hw.hfcsx.trm |= 0x20; /* enable echo chan */ in hfcsx_auxcmd()
626 cs->hw.hfcsx.int_m1 |= HFCSX_INTS_B2REC; in hfcsx_auxcmd()
630 cs->hw.hfcsx.trm &= ~0x20; /* disable echo chan */ in hfcsx_auxcmd()
631 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_B2REC; in hfcsx_auxcmd()
633 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA; in hfcsx_auxcmd()
634 cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA; in hfcsx_auxcmd()
635 cs->hw.hfcsx.conn |= 0x10; /* B2-IOM -> B2-ST */ in hfcsx_auxcmd()
636 cs->hw.hfcsx.ctmt &= ~2; in hfcsx_auxcmd()
638 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt); in hfcsx_auxcmd()
639 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r); in hfcsx_auxcmd()
640 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); in hfcsx_auxcmd()
641 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); in hfcsx_auxcmd()
642 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm); in hfcsx_auxcmd()
643 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in hfcsx_auxcmd()
703 if (!(cs->hw.hfcsx.int_m2 & 0x08)) in hfcsx_interrupt()
719 val &= cs->hw.hfcsx.int_m1; in hfcsx_interrupt()
723 debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcsx.ph_state, in hfcsx_interrupt()
725 cs->dc.hfcsx.ph_state = exval; in hfcsx_interrupt()
730 if (cs->hw.hfcsx.nt_mode) { in hfcsx_interrupt()
731 if ((--cs->hw.hfcsx.nt_timer) < 0) in hfcsx_interrupt()
735 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER); in hfcsx_interrupt()
739 cs->hw.hfcsx.int_s1 |= val; in hfcsx_interrupt()
743 if (cs->hw.hfcsx.int_s1 & 0x18) { in hfcsx_interrupt()
745 val = cs->hw.hfcsx.int_s1; in hfcsx_interrupt()
746 cs->hw.hfcsx.int_s1 = exval; in hfcsx_interrupt()
749 if (!(bcs = Sel_BCS(cs, cs->hw.hfcsx.bswapped ? 1 : 0))) { in hfcsx_interrupt()
765 if (!(bcs = Sel_BCS(cs, cs->hw.hfcsx.bswapped ? 1 : 0))) { in hfcsx_interrupt()
847 if (cs->hw.hfcsx.int_s1 && count--) { in hfcsx_interrupt()
848 val = cs->hw.hfcsx.int_s1; in hfcsx_interrupt()
849 cs->hw.hfcsx.int_s1 = 0; in hfcsx_interrupt()
948 cs->hw.hfcsx.mst_m |= HFCSX_MASTER; in HFCSX_l1hw()
949 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); in HFCSX_l1hw()
961 cs->hw.hfcsx.mst_m &= ~HFCSX_MASTER; in HFCSX_l1hw()
962 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); in HFCSX_l1hw()
967 cs->hw.hfcsx.mst_m |= HFCSX_MASTER; in HFCSX_l1hw()
968 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); in HFCSX_l1hw()
977 cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~7) | 1; in HFCSX_l1hw()
978 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); in HFCSX_l1hw()
983 cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~0x38) | 0x08; in HFCSX_l1hw()
984 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); in HFCSX_l1hw()
992 cs->hw.hfcsx.trm |= 0x80; /* enable IOM-loop */ in HFCSX_l1hw()
993 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm); in HFCSX_l1hw()
1043 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */ in mode_hfcsx()
1044 cs->hw.hfcsx.sctrl_e &= ~0x80; in mode_hfcsx()
1048 cs->hw.hfcsx.bswapped = 1; /* B1 and B2 exchanged */ in mode_hfcsx()
1049 cs->hw.hfcsx.sctrl_e |= 0x80; in mode_hfcsx()
1051 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */ in mode_hfcsx()
1052 cs->hw.hfcsx.sctrl_e &= ~0x80; in mode_hfcsx()
1056 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */ in mode_hfcsx()
1057 cs->hw.hfcsx.sctrl_e &= ~0x80; in mode_hfcsx()
1063 cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA; in mode_hfcsx()
1064 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA; in mode_hfcsx()
1066 cs->hw.hfcsx.sctrl &= ~SCTRL_B1_ENA; in mode_hfcsx()
1067 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B1_ENA; in mode_hfcsx()
1070 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); in mode_hfcsx()
1072 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); in mode_hfcsx()
1077 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA; in mode_hfcsx()
1078 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA; in mode_hfcsx()
1080 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA; in mode_hfcsx()
1081 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA; in mode_hfcsx()
1084 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); in mode_hfcsx()
1085 cs->hw.hfcsx.ctmt |= 2; in mode_hfcsx()
1086 cs->hw.hfcsx.conn &= ~0x18; in mode_hfcsx()
1088 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); in mode_hfcsx()
1089 cs->hw.hfcsx.ctmt |= 1; in mode_hfcsx()
1090 cs->hw.hfcsx.conn &= ~0x03; in mode_hfcsx()
1095 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA; in mode_hfcsx()
1096 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA; in mode_hfcsx()
1098 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA; in mode_hfcsx()
1099 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA; in mode_hfcsx()
1102 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); in mode_hfcsx()
1103 cs->hw.hfcsx.ctmt &= ~2; in mode_hfcsx()
1104 cs->hw.hfcsx.conn &= ~0x18; in mode_hfcsx()
1106 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); in mode_hfcsx()
1107 cs->hw.hfcsx.ctmt &= ~1; in mode_hfcsx()
1108 cs->hw.hfcsx.conn &= ~0x03; in mode_hfcsx()
1113 cs->hw.hfcsx.conn |= 0x10; in mode_hfcsx()
1114 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA; in mode_hfcsx()
1115 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA; in mode_hfcsx()
1116 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); in mode_hfcsx()
1118 cs->hw.hfcsx.conn |= 0x02; in mode_hfcsx()
1119 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA; in mode_hfcsx()
1120 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA; in mode_hfcsx()
1121 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); in mode_hfcsx()
1125 Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e); in mode_hfcsx()
1126 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in mode_hfcsx()
1127 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); in mode_hfcsx()
1128 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r); in mode_hfcsx()
1129 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt); in mode_hfcsx()
1130 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); in mode_hfcsx()
1261 if (!cs->hw.hfcsx.nt_mode) in hfcsx_bh()
1262 switch (cs->dc.hfcsx.ph_state) { in hfcsx_bh()
1281 switch (cs->dc.hfcsx.ph_state) { in hfcsx_bh()
1284 if (cs->hw.hfcsx.nt_timer < 0) { in hfcsx_bh()
1285 cs->hw.hfcsx.nt_timer = 0; in hfcsx_bh()
1286 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER; in hfcsx_bh()
1287 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in hfcsx_bh()
1294 cs->dc.hfcsx.ph_state = 4; in hfcsx_bh()
1296 cs->hw.hfcsx.int_m1 |= HFCSX_INTS_TIMER; in hfcsx_bh()
1297 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in hfcsx_bh()
1298 cs->hw.hfcsx.ctmt &= ~HFCSX_AUTO_TIMER; in hfcsx_bh()
1299 cs->hw.hfcsx.ctmt |= HFCSX_TIM3_125; in hfcsx_bh()
1300 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER); in hfcsx_bh()
1301 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER); in hfcsx_bh()
1302 cs->hw.hfcsx.nt_timer = NT_T1_COUNT; in hfcsx_bh()
1311 cs->hw.hfcsx.nt_timer = 0; in hfcsx_bh()
1312 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER; in hfcsx_bh()
1313 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in hfcsx_bh()
1371 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER; in hfcsx_card_msg()
1372 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in hfcsx_card_msg()
1374 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); in hfcsx_card_msg()
1445 cs->hw.hfcsx.base = card->para[1] & 0xfffe; in setup_hfcsx()
1447 cs->hw.hfcsx.int_s1 = 0; in setup_hfcsx()
1448 cs->dc.hfcsx.ph_state = 0; in setup_hfcsx()
1449 cs->hw.hfcsx.fifo = 255; in setup_hfcsx()
1452 if ((!cs->hw.hfcsx.base) || !request_region(cs->hw.hfcsx.base, 2, "HFCSX isdn")) { in setup_hfcsx()
1455 cs->hw.hfcsx.base); in setup_hfcsx()
1458 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.base & 0xFF); in setup_hfcsx()
1459 byteout(cs->hw.hfcsx.base + 1, in setup_hfcsx()
1460 ((cs->hw.hfcsx.base >> 8) & 3) | 0x54); in setup_hfcsx()
1462 cs->hw.hfcsx.chip = Read_hfc(cs, HFCSX_CHIP_ID); in setup_hfcsx()
1463 switch (cs->hw.hfcsx.chip >> 4) { in setup_hfcsx()
1473 cs->hw.hfcsx.chip >> 4); in setup_hfcsx()
1474 release_region(cs->hw.hfcsx.base, 2); in setup_hfcsx()
1480 release_region(cs->hw.hfcsx.base, 2); in setup_hfcsx()
1483 if (!(cs->hw.hfcsx.extra = (void *) in setup_hfcsx()
1485 release_region(cs->hw.hfcsx.base, 2); in setup_hfcsx()
1490 tmp[0], (u_int) cs->hw.hfcsx.base, cs->irq, HZ); in setup_hfcsx()
1491 cs->hw.hfcsx.int_m2 = 0; /* disable alle interrupts */ in setup_hfcsx()
1492 cs->hw.hfcsx.int_m1 = 0; in setup_hfcsx()
1493 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in setup_hfcsx()
1494 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); in setup_hfcsx()
1510 cs->hw.hfcsx.timer.function = (void *) hfcsx_Timer; in setup_hfcsx()
1511 cs->hw.hfcsx.timer.data = (long) cs; in setup_hfcsx()
1512 cs->hw.hfcsx.b_fifo_size = 0; /* fifo size still unknown */ in setup_hfcsx()
1513 cs->hw.hfcsx.cirm = ccd_sp_irqtab[cs->irq & 0xF]; /* RAM not evaluated */ in setup_hfcsx()
1514 init_timer(&cs->hw.hfcsx.timer); in setup_hfcsx()