1107 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1117 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1127 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1137 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1147 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1157 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1167 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1177 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1187 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1197 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1207 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1217 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1227 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1237 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1247 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1257 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1267 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1277 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1287 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |  in si_tiling_mode_table_init()
1297 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1307 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1317 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1327 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1346 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1356 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1366 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1376 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1386 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1396 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1406 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1416 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1426 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1436 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1446 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1456 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1466 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1476 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1486 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1496 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1506 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1516 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1526 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |  in si_tiling_mode_table_init()
1536 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1546 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1556 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
1566 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()