861 	int pipeA = (psb_intel_crtc->pipe == 0);  in psb_intel_crtc_save()  local
870 	crtc_state->saveDSPCNTR = REG_READ(pipeA ? DSPACNTR : DSPBCNTR);  in psb_intel_crtc_save()
871 	crtc_state->savePIPECONF = REG_READ(pipeA ? PIPEACONF : PIPEBCONF);  in psb_intel_crtc_save()
872 	crtc_state->savePIPESRC = REG_READ(pipeA ? PIPEASRC : PIPEBSRC);  in psb_intel_crtc_save()
873 	crtc_state->saveFP0 = REG_READ(pipeA ? FPA0 : FPB0);  in psb_intel_crtc_save()
874 	crtc_state->saveFP1 = REG_READ(pipeA ? FPA1 : FPB1);  in psb_intel_crtc_save()
875 	crtc_state->saveDPLL = REG_READ(pipeA ? DPLL_A : DPLL_B);  in psb_intel_crtc_save()
876 	crtc_state->saveHTOTAL = REG_READ(pipeA ? HTOTAL_A : HTOTAL_B);  in psb_intel_crtc_save()
877 	crtc_state->saveHBLANK = REG_READ(pipeA ? HBLANK_A : HBLANK_B);  in psb_intel_crtc_save()
878 	crtc_state->saveHSYNC = REG_READ(pipeA ? HSYNC_A : HSYNC_B);  in psb_intel_crtc_save()
879 	crtc_state->saveVTOTAL = REG_READ(pipeA ? VTOTAL_A : VTOTAL_B);  in psb_intel_crtc_save()
880 	crtc_state->saveVBLANK = REG_READ(pipeA ? VBLANK_A : VBLANK_B);  in psb_intel_crtc_save()
881 	crtc_state->saveVSYNC = REG_READ(pipeA ? VSYNC_A : VSYNC_B);  in psb_intel_crtc_save()
882 	crtc_state->saveDSPSTRIDE = REG_READ(pipeA ? DSPASTRIDE : DSPBSTRIDE);  in psb_intel_crtc_save()
885 	crtc_state->saveDSPSIZE = REG_READ(pipeA ? DSPASIZE : DSPBSIZE);  in psb_intel_crtc_save()
886 	crtc_state->saveDSPPOS = REG_READ(pipeA ? DSPAPOS : DSPBPOS);  in psb_intel_crtc_save()
888 	crtc_state->saveDSPBASE = REG_READ(pipeA ? DSPABASE : DSPBBASE);  in psb_intel_crtc_save()
890 	paletteReg = pipeA ? PALETTE_A : PALETTE_B;  in psb_intel_crtc_save()
906 	int pipeA = (psb_intel_crtc->pipe == 0);  in psb_intel_crtc_restore()  local
916 		REG_WRITE(pipeA ? DPLL_A : DPLL_B,  in psb_intel_crtc_restore()
918 		REG_READ(pipeA ? DPLL_A : DPLL_B);  in psb_intel_crtc_restore()
922 	REG_WRITE(pipeA ? FPA0 : FPB0, crtc_state->saveFP0);  in psb_intel_crtc_restore()
923 	REG_READ(pipeA ? FPA0 : FPB0);  in psb_intel_crtc_restore()
925 	REG_WRITE(pipeA ? FPA1 : FPB1, crtc_state->saveFP1);  in psb_intel_crtc_restore()
926 	REG_READ(pipeA ? FPA1 : FPB1);  in psb_intel_crtc_restore()
928 	REG_WRITE(pipeA ? DPLL_A : DPLL_B, crtc_state->saveDPLL);  in psb_intel_crtc_restore()
929 	REG_READ(pipeA ? DPLL_A : DPLL_B);  in psb_intel_crtc_restore()
932 	REG_WRITE(pipeA ? HTOTAL_A : HTOTAL_B, crtc_state->saveHTOTAL);  in psb_intel_crtc_restore()
933 	REG_WRITE(pipeA ? HBLANK_A : HBLANK_B, crtc_state->saveHBLANK);  in psb_intel_crtc_restore()
934 	REG_WRITE(pipeA ? HSYNC_A : HSYNC_B, crtc_state->saveHSYNC);  in psb_intel_crtc_restore()
935 	REG_WRITE(pipeA ? VTOTAL_A : VTOTAL_B, crtc_state->saveVTOTAL);  in psb_intel_crtc_restore()
936 	REG_WRITE(pipeA ? VBLANK_A : VBLANK_B, crtc_state->saveVBLANK);  in psb_intel_crtc_restore()
937 	REG_WRITE(pipeA ? VSYNC_A : VSYNC_B, crtc_state->saveVSYNC);  in psb_intel_crtc_restore()
938 	REG_WRITE(pipeA ? DSPASTRIDE : DSPBSTRIDE, crtc_state->saveDSPSTRIDE);  in psb_intel_crtc_restore()
940 	REG_WRITE(pipeA ? DSPASIZE : DSPBSIZE, crtc_state->saveDSPSIZE);  in psb_intel_crtc_restore()
941 	REG_WRITE(pipeA ? DSPAPOS : DSPBPOS, crtc_state->saveDSPPOS);  in psb_intel_crtc_restore()
943 	REG_WRITE(pipeA ? PIPEASRC : PIPEBSRC, crtc_state->savePIPESRC);  in psb_intel_crtc_restore()
944 	REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE);  in psb_intel_crtc_restore()
945 	REG_WRITE(pipeA ? PIPEACONF : PIPEBCONF, crtc_state->savePIPECONF);  in psb_intel_crtc_restore()
949 	REG_WRITE(pipeA ? DSPACNTR : DSPBCNTR, crtc_state->saveDSPCNTR);  in psb_intel_crtc_restore()
950 	REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE);  in psb_intel_crtc_restore()
954 	paletteReg = pipeA ? PALETTE_A : PALETTE_B;  in psb_intel_crtc_restore()