Lines Matching refs:csa
53 ch0_cnt = ctx->csa.spu_chnlcnt_RW[0]; in gen_spu_event()
54 ch0_data = ctx->csa.spu_chnldata_RW[0]; in gen_spu_event()
55 ch1_data = ctx->csa.spu_chnldata_RW[1]; in gen_spu_event()
56 ctx->csa.spu_chnldata_RW[0] |= event; in gen_spu_event()
58 ctx->csa.spu_chnlcnt_RW[0] = 1; in gen_spu_event()
67 spin_lock(&ctx->csa.register_lock); in spu_backing_mbox_read()
68 mbox_stat = ctx->csa.prob.mb_stat_R; in spu_backing_mbox_read()
74 *data = ctx->csa.prob.pu_mb_R; in spu_backing_mbox_read()
75 ctx->csa.prob.mb_stat_R &= ~(0x0000ff); in spu_backing_mbox_read()
76 ctx->csa.spu_chnlcnt_RW[28] = 1; in spu_backing_mbox_read()
80 spin_unlock(&ctx->csa.register_lock); in spu_backing_mbox_read()
86 return ctx->csa.prob.mb_stat_R; in spu_backing_mbox_stat_read()
96 spin_lock_irq(&ctx->csa.register_lock); in spu_backing_mbox_stat_poll()
97 stat = ctx->csa.prob.mb_stat_R; in spu_backing_mbox_stat_poll()
108 ctx->csa.priv1.int_stat_class2_RW &= in spu_backing_mbox_stat_poll()
110 ctx->csa.priv1.int_mask_class2_RW |= in spu_backing_mbox_stat_poll()
118 ctx->csa.priv1.int_stat_class2_RW &= in spu_backing_mbox_stat_poll()
120 ctx->csa.priv1.int_mask_class2_RW |= in spu_backing_mbox_stat_poll()
124 spin_unlock_irq(&ctx->csa.register_lock); in spu_backing_mbox_stat_poll()
132 spin_lock(&ctx->csa.register_lock); in spu_backing_ibox_read()
133 if (ctx->csa.prob.mb_stat_R & 0xff0000) { in spu_backing_ibox_read()
138 *data = ctx->csa.priv2.puint_mb_R; in spu_backing_ibox_read()
139 ctx->csa.prob.mb_stat_R &= ~(0xff0000); in spu_backing_ibox_read()
140 ctx->csa.spu_chnlcnt_RW[30] = 1; in spu_backing_ibox_read()
145 ctx->csa.priv1.int_mask_class2_RW |= CLASS2_ENABLE_MAILBOX_INTR; in spu_backing_ibox_read()
148 spin_unlock(&ctx->csa.register_lock); in spu_backing_ibox_read()
156 spin_lock(&ctx->csa.register_lock); in spu_backing_wbox_write()
157 if ((ctx->csa.prob.mb_stat_R) & 0x00ff00) { in spu_backing_wbox_write()
158 int slot = ctx->csa.spu_chnlcnt_RW[29]; in spu_backing_wbox_write()
159 int avail = (ctx->csa.prob.mb_stat_R & 0x00ff00) >> 8; in spu_backing_wbox_write()
166 ctx->csa.spu_mailbox_data[slot] = data; in spu_backing_wbox_write()
167 ctx->csa.spu_chnlcnt_RW[29] = ++slot; in spu_backing_wbox_write()
168 ctx->csa.prob.mb_stat_R &= ~(0x00ff00); in spu_backing_wbox_write()
169 ctx->csa.prob.mb_stat_R |= (((4 - slot) & 0xff) << 8); in spu_backing_wbox_write()
175 ctx->csa.priv1.int_mask_class2_RW |= in spu_backing_wbox_write()
179 spin_unlock(&ctx->csa.register_lock); in spu_backing_wbox_write()
185 return ctx->csa.spu_chnldata_RW[3]; in spu_backing_signal1_read()
190 spin_lock(&ctx->csa.register_lock); in spu_backing_signal1_write()
191 if (ctx->csa.priv2.spu_cfg_RW & 0x1) in spu_backing_signal1_write()
192 ctx->csa.spu_chnldata_RW[3] |= data; in spu_backing_signal1_write()
194 ctx->csa.spu_chnldata_RW[3] = data; in spu_backing_signal1_write()
195 ctx->csa.spu_chnlcnt_RW[3] = 1; in spu_backing_signal1_write()
197 spin_unlock(&ctx->csa.register_lock); in spu_backing_signal1_write()
202 return ctx->csa.spu_chnldata_RW[4]; in spu_backing_signal2_read()
207 spin_lock(&ctx->csa.register_lock); in spu_backing_signal2_write()
208 if (ctx->csa.priv2.spu_cfg_RW & 0x2) in spu_backing_signal2_write()
209 ctx->csa.spu_chnldata_RW[4] |= data; in spu_backing_signal2_write()
211 ctx->csa.spu_chnldata_RW[4] = data; in spu_backing_signal2_write()
212 ctx->csa.spu_chnlcnt_RW[4] = 1; in spu_backing_signal2_write()
214 spin_unlock(&ctx->csa.register_lock); in spu_backing_signal2_write()
221 spin_lock(&ctx->csa.register_lock); in spu_backing_signal1_type_set()
222 tmp = ctx->csa.priv2.spu_cfg_RW; in spu_backing_signal1_type_set()
227 ctx->csa.priv2.spu_cfg_RW = tmp; in spu_backing_signal1_type_set()
228 spin_unlock(&ctx->csa.register_lock); in spu_backing_signal1_type_set()
233 return ((ctx->csa.priv2.spu_cfg_RW & 1) != 0); in spu_backing_signal1_type_get()
240 spin_lock(&ctx->csa.register_lock); in spu_backing_signal2_type_set()
241 tmp = ctx->csa.priv2.spu_cfg_RW; in spu_backing_signal2_type_set()
246 ctx->csa.priv2.spu_cfg_RW = tmp; in spu_backing_signal2_type_set()
247 spin_unlock(&ctx->csa.register_lock); in spu_backing_signal2_type_set()
252 return ((ctx->csa.priv2.spu_cfg_RW & 2) != 0); in spu_backing_signal2_type_get()
257 return ctx->csa.prob.spu_npc_RW; in spu_backing_npc_read()
262 ctx->csa.prob.spu_npc_RW = val; in spu_backing_npc_write()
267 return ctx->csa.prob.spu_status_R; in spu_backing_status_read()
272 return ctx->csa.lscsa->ls; in spu_backing_get_ls()
277 ctx->csa.priv2.spu_privcntl_RW = val; in spu_backing_privcntl_write()
282 return ctx->csa.prob.spu_runcntl_RW; in spu_backing_runcntl_read()
287 spin_lock(&ctx->csa.register_lock); in spu_backing_runcntl_write()
288 ctx->csa.prob.spu_runcntl_RW = val; in spu_backing_runcntl_write()
290 ctx->csa.prob.spu_status_R &= in spu_backing_runcntl_write()
296 ctx->csa.prob.spu_status_R |= SPU_STATUS_RUNNING; in spu_backing_runcntl_write()
298 ctx->csa.prob.spu_status_R &= ~SPU_STATUS_RUNNING; in spu_backing_runcntl_write()
300 spin_unlock(&ctx->csa.register_lock); in spu_backing_runcntl_write()
310 struct spu_state *csa = &ctx->csa; in spu_backing_master_start() local
313 spin_lock(&csa->register_lock); in spu_backing_master_start()
314 sr1 = csa->priv1.mfc_sr1_RW | MFC_STATE1_MASTER_RUN_CONTROL_MASK; in spu_backing_master_start()
315 csa->priv1.mfc_sr1_RW = sr1; in spu_backing_master_start()
316 spin_unlock(&csa->register_lock); in spu_backing_master_start()
321 struct spu_state *csa = &ctx->csa; in spu_backing_master_stop() local
324 spin_lock(&csa->register_lock); in spu_backing_master_stop()
325 sr1 = csa->priv1.mfc_sr1_RW & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK; in spu_backing_master_stop()
326 csa->priv1.mfc_sr1_RW = sr1; in spu_backing_master_stop()
327 spin_unlock(&csa->register_lock); in spu_backing_master_stop()
333 struct spu_problem_collapsed *prob = &ctx->csa.prob; in spu_backing_set_mfc_query()
336 spin_lock(&ctx->csa.register_lock); in spu_backing_set_mfc_query()
349 ctx->csa.prob.dma_tagstatus_R &= mask; in spu_backing_set_mfc_query()
351 spin_unlock(&ctx->csa.register_lock); in spu_backing_set_mfc_query()
358 return ctx->csa.prob.dma_tagstatus_R; in spu_backing_read_mfc_tagstatus()
363 return ctx->csa.prob.dma_qstatus_R; in spu_backing_get_mfc_free_elements()
371 spin_lock(&ctx->csa.register_lock); in spu_backing_send_mfc_command()
374 spin_unlock(&ctx->csa.register_lock); in spu_backing_send_mfc_command()
381 ctx->csa.priv2.mfc_control_RW |= MFC_CNTL_RESTART_DMA_COMMAND; in spu_backing_restart_dma()