Lines Matching refs:uint
19 #define CPM_CR_RST ((uint)0x80000000)
20 #define CPM_CR_PAGE ((uint)0x7c000000)
21 #define CPM_CR_SBLOCK ((uint)0x03e00000)
22 #define CPM_CR_FLG ((uint)0x00010000)
23 #define CPM_CR_MCN ((uint)0x00003fc0)
24 #define CPM_CR_OPCODE ((uint)0x0000000f)
97 #define CPM_BRG_RST ((uint)0x00020000)
98 #define CPM_BRG_EN ((uint)0x00010000)
99 #define CPM_BRG_EXTC_INT ((uint)0x00000000)
100 #define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
101 #define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000)
102 #define CPM_BRG_ATB ((uint)0x00002000)
103 #define CPM_BRG_CD_MASK ((uint)0x00001ffe)
104 #define CPM_BRG_DIV16 ((uint)0x00000001)
109 extern void __cpm2_setbrg(uint brg, uint rate, uint clk, int div16, int src);
114 static inline void cpm_setbrg(uint brg, uint rate) in cpm_setbrg()
122 static inline void cpm2_fastbrg(uint brg, uint rate, int div16) in cpm2_fastbrg()
129 #define PROFF_SCC1 ((uint)0x8000)
130 #define PROFF_SCC2 ((uint)0x8100)
131 #define PROFF_SCC3 ((uint)0x8200)
132 #define PROFF_SCC4 ((uint)0x8300)
133 #define PROFF_FCC1 ((uint)0x8400)
134 #define PROFF_FCC2 ((uint)0x8500)
135 #define PROFF_FCC3 ((uint)0x8600)
136 #define PROFF_MCC1 ((uint)0x8700)
137 #define PROFF_SMC1_BASE ((uint)0x87fc)
138 #define PROFF_IDMA1_BASE ((uint)0x87fe)
139 #define PROFF_MCC2 ((uint)0x8800)
140 #define PROFF_SMC2_BASE ((uint)0x88fc)
141 #define PROFF_IDMA2_BASE ((uint)0x88fe)
142 #define PROFF_SPI_BASE ((uint)0x89fc)
143 #define PROFF_IDMA3_BASE ((uint)0x89fe)
144 #define PROFF_TIMERS ((uint)0x8ae0)
145 #define PROFF_REVNUM ((uint)0x8af0)
146 #define PROFF_RAND ((uint)0x8af8)
147 #define PROFF_I2C_BASE ((uint)0x8afc)
148 #define PROFF_IDMA4_BASE ((uint)0x8afe)
150 #define PROFF_SCC_SIZE ((uint)0x100)
151 #define PROFF_FCC_SIZE ((uint)0x100)
152 #define PROFF_SMC_SIZE ((uint)64)
172 uint smc_rstate; /* Internal */
173 uint smc_idp; /* Internal */
176 uint smc_rxtmp; /* Internal */
177 uint smc_tstate; /* Internal */
178 uint smc_tdp; /* Internal */
181 uint smc_txtmp; /* Internal */
188 uint smc_stmp; /* SDMA Temp */
219 #define SCC_GSMRH_IRP ((uint)0x00040000)
220 #define SCC_GSMRH_GDE ((uint)0x00010000)
221 #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
222 #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
223 #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
224 #define SCC_GSMRH_REVD ((uint)0x00002000)
225 #define SCC_GSMRH_TRX ((uint)0x00001000)
226 #define SCC_GSMRH_TTX ((uint)0x00000800)
227 #define SCC_GSMRH_CDP ((uint)0x00000400)
228 #define SCC_GSMRH_CTSP ((uint)0x00000200)
229 #define SCC_GSMRH_CDS ((uint)0x00000100)
230 #define SCC_GSMRH_CTSS ((uint)0x00000080)
231 #define SCC_GSMRH_TFL ((uint)0x00000040)
232 #define SCC_GSMRH_RFW ((uint)0x00000020)
233 #define SCC_GSMRH_TXSY ((uint)0x00000010)
234 #define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
235 #define SCC_GSMRH_SYNL8 ((uint)0x00000008)
236 #define SCC_GSMRH_SYNL4 ((uint)0x00000004)
237 #define SCC_GSMRH_RTSM ((uint)0x00000002)
238 #define SCC_GSMRH_RSYN ((uint)0x00000001)
240 #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
241 #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
242 #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
243 #define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
244 #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
245 #define SCC_GSMRL_TCI ((uint)0x10000000)
246 #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
247 #define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
248 #define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
249 #define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
250 #define SCC_GSMRL_RINV ((uint)0x02000000)
251 #define SCC_GSMRL_TINV ((uint)0x01000000)
252 #define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
253 #define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
254 #define SCC_GSMRL_TPL_48 ((uint)0x00800000)
255 #define SCC_GSMRL_TPL_32 ((uint)0x00600000)
256 #define SCC_GSMRL_TPL_16 ((uint)0x00400000)
257 #define SCC_GSMRL_TPL_8 ((uint)0x00200000)
258 #define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
259 #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
260 #define SCC_GSMRL_TPP_01 ((uint)0x00100000)
261 #define SCC_GSMRL_TPP_10 ((uint)0x00080000)
262 #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
263 #define SCC_GSMRL_TEND ((uint)0x00040000)
264 #define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
265 #define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
266 #define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
267 #define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
268 #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
269 #define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
270 #define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
271 #define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
272 #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
273 #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
274 #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
275 #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
276 #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
277 #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
278 #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
279 #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
280 #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
281 #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
282 #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
283 #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
284 #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
285 #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
286 #define SCC_GSMRL_ENR ((uint)0x00000020)
287 #define SCC_GSMRL_ENT ((uint)0x00000010)
288 #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
289 #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
290 #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
291 #define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
292 #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
293 #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
294 #define SCC_GSMRL_MODE_UART ((uint)0x00000004)
295 #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
296 #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
297 #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
314 uint scc_rstate; /* Internal */
315 uint scc_idp; /* Internal */
318 uint scc_rxtmp; /* Internal */
319 uint scc_tstate; /* Internal */
320 uint scc_tdp; /* Internal */
323 uint scc_txtmp; /* Internal */
324 uint scc_rcrc; /* Internal */
325 uint scc_tcrc; /* Internal */
337 uint sen_cpres; /* Preset CRC */
338 uint sen_cmask; /* Constant mask for CRC */
339 uint sen_crcec; /* CRC Error counter */
340 uint sen_alec; /* alignment error counter */
341 uint sen_disfc; /* discard frame counter */
356 uint sen_tbuf0data0; /* Save area 0 - current frame */
357 uint sen_tbuf0data1; /* Save area 1 - current frame */
358 uint sen_tbuf0rba; /* Internal */
359 uint sen_tbuf0crc; /* Internal */
368 uint sen_tbuf1data0; /* Save area 0 - current frame */
369 uint sen_tbuf1data1; /* Save area 1 - current frame */
370 uint sen_tbuf1rba; /* Internal */
371 uint sen_tbuf1crc; /* Internal */
418 uint scc_res1; /* Reserved */
419 uint scc_res2; /* Reserved */
479 uint st_cpres; /* Preset CRC */
480 uint st_cmask; /* Constant mask for CRC */
485 #define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
486 #define FCC_GFMR_DIAG_LE ((uint)0x40000000)
487 #define FCC_GFMR_DIAG_AE ((uint)0x80000000)
488 #define FCC_GFMR_DIAG_ALE ((uint)0xc0000000)
489 #define FCC_GFMR_TCI ((uint)0x20000000)
490 #define FCC_GFMR_TRX ((uint)0x10000000)
491 #define FCC_GFMR_TTX ((uint)0x08000000)
492 #define FCC_GFMR_TTX ((uint)0x08000000)
493 #define FCC_GFMR_CDP ((uint)0x04000000)
494 #define FCC_GFMR_CTSP ((uint)0x02000000)
495 #define FCC_GFMR_CDS ((uint)0x01000000)
496 #define FCC_GFMR_CTSS ((uint)0x00800000)
497 #define FCC_GFMR_SYNL_NONE ((uint)0x00000000)
498 #define FCC_GFMR_SYNL_AUTO ((uint)0x00004000)
499 #define FCC_GFMR_SYNL_8 ((uint)0x00008000)
500 #define FCC_GFMR_SYNL_16 ((uint)0x0000c000)
501 #define FCC_GFMR_RTSM ((uint)0x00002000)
502 #define FCC_GFMR_RENC_NRZ ((uint)0x00000000)
503 #define FCC_GFMR_RENC_NRZI ((uint)0x00000800)
504 #define FCC_GFMR_REVD ((uint)0x00000400)
505 #define FCC_GFMR_TENC_NRZ ((uint)0x00000000)
506 #define FCC_GFMR_TENC_NRZI ((uint)0x00000100)
507 #define FCC_GFMR_TCRC_16 ((uint)0x00000000)
508 #define FCC_GFMR_TCRC_32 ((uint)0x00000080)
509 #define FCC_GFMR_ENR ((uint)0x00000020)
510 #define FCC_GFMR_ENT ((uint)0x00000010)
511 #define FCC_GFMR_MODE_ENET ((uint)0x0000000c)
512 #define FCC_GFMR_MODE_ATM ((uint)0x0000000a)
513 #define FCC_GFMR_MODE_HDLC ((uint)0x00000000)
522 uint fcc_rstate; /* Upper byte is Func code, must be set */
523 uint fcc_rbase; /* Receive BD base */
526 uint fcc_rdptr; /* RxBD internal data pointer */
527 uint fcc_tstate; /* Upper byte is Func code, must be set */
528 uint fcc_tbase; /* Transmit BD base */
531 uint fcc_tdptr; /* TxBD internal data pointer */
532 uint fcc_rbptr; /* Rx BD Internal buf pointer */
533 uint fcc_tbptr; /* Tx BD Internal buf pointer */
534 uint fcc_rcrc; /* Rx temp CRC */
535 uint fcc_res2;
536 uint fcc_tcrc; /* Tx temp CRC */
544 uint fen_statbuf; /* Internal status buffer */
545 uint fen_camptr; /* CAM address */
546 uint fen_cmask; /* Constant mask for CRC */
547 uint fen_cpres; /* Preset CRC */
548 uint fen_crcec; /* CRC Error counter */
549 uint fen_alec; /* alignment error counter */
550 uint fen_disfc; /* discard frame counter */
555 uint fen_gaddrh; /* Group address filter, high 32-bits */
556 uint fen_gaddrl; /* Group address filter, low 32-bits */
559 uint fen_tfcptr;
568 uint fen_ibdbase[8]; /* Internal use */
569 uint fen_iaddrh; /* Individual address filter */
570 uint fen_iaddrl;
583 uint fen_octc; /* Total octect counter */
584 uint fen_colc; /* Total collision counter */
585 uint fen_broc; /* Total broadcast packet counter */
586 uint fen_mulc; /* Total multicast packet count */
587 uint fen_uspc; /* Total packets < 64 bytes */
588 uint fen_frgc; /* Total packets < 64 bytes with errors */
589 uint fen_ospc; /* Total packets > 1518 */
590 uint fen_jbrc; /* Total packets > 1518 with errors */
591 uint fen_p64c; /* Total packets == 64 bytes */
592 uint fen_p65c; /* Total packets 64 < bytes <= 127 */
593 uint fen_p128c; /* Total packets 127 < bytes <= 255 */
594 uint fen_p256c; /* Total packets 256 < bytes <= 511 */
595 uint fen_p512c; /* Total packets 512 < bytes <= 1023 */
596 uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */
597 uint fen_cambuf; /* Internal CAM buffer poiner */
615 #define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */
616 #define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */
617 #define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */
618 #define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */
619 #define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */
620 #define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */
621 #define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */
622 #define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */
623 #define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */
624 #define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */
625 #define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */
626 #define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */
627 #define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */
637 uint iic_rstate; /* Internal */
638 uint iic_rdp; /* Internal */
641 uint iic_rxtmp; /* Internal */
642 uint iic_tstate; /* Internal */
643 uint iic_tdp; /* Internal */
646 uint iic_txtmp; /* Internal */
666 uint bd_cnt; /* internal byte count */
667 uint s_ptr; /* source internal data pointer */
668 uint d_ptr; /* destination internal data pointer */
669 uint istate; /* internal state */
697 uint flags;
698 uint len; /* data length */
699 uint src; /* source data buffer pointer */
700 uint dst; /* destination data buffer pointer */
705 #define IDMA_BD_V ((uint)0x80000000) /* valid */
706 #define IDMA_BD_W ((uint)0x20000000) /* wrap */
707 #define IDMA_BD_I ((uint)0x10000000) /* interrupt */
708 #define IDMA_BD_L ((uint)0x08000000) /* last */
709 #define IDMA_BD_CM ((uint)0x02000000) /* continuous mode */
710 #define IDMA_BD_SDN ((uint)0x00400000) /* source done */
711 #define IDMA_BD_DDN ((uint)0x00200000) /* destination done */
712 #define IDMA_BD_DGBL ((uint)0x00100000) /* destination global */
713 #define IDMA_BD_DBO_LE ((uint)0x00040000) /* little-end dest byte order */
714 #define IDMA_BD_DBO_BE ((uint)0x00080000) /* big-end dest byte order */
715 #define IDMA_BD_DDTB ((uint)0x00010000) /* destination data bus */
716 #define IDMA_BD_SGBL ((uint)0x00002000) /* source global */
717 #define IDMA_BD_SBO_LE ((uint)0x00000800) /* little-end src byte order */
718 #define IDMA_BD_SBO_BE ((uint)0x00001000) /* big-end src byte order */
719 #define IDMA_BD_SDTB ((uint)0x00000200) /* source data bus */
739 #define RCCR_TIME ((uint)0x80000000) /* timer enable */
740 #define RCCR_TIMEP_MASK ((uint)0x3f000000) /* mask for timer period bit field */
741 #define RCCR_DR0M ((uint)0x00800000) /* IDMA0 request mode */
742 #define RCCR_DR1M ((uint)0x00400000) /* IDMA1 request mode */
743 #define RCCR_DR2M ((uint)0x00000080) /* IDMA2 request mode */
744 #define RCCR_DR3M ((uint)0x00000040) /* IDMA3 request mode */
745 #define RCCR_DR0QP_MASK ((uint)0x00300000) /* mask for IDMA0 req priority */
746 #define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */
747 #define RCCR_DR0QP_MED ((uint)0x00100000) /* IDMA0 has medium req priority */
748 #define RCCR_DR0QP_LOW ((uint)0x00200000) /* IDMA0 has low req priority */
749 #define RCCR_DR1QP_MASK ((uint)0x00030000) /* mask for IDMA1 req priority */
750 #define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */
751 #define RCCR_DR1QP_MED ((uint)0x00010000) /* IDMA1 has medium req priority */
752 #define RCCR_DR1QP_LOW ((uint)0x00020000) /* IDMA1 has low req priority */
753 #define RCCR_DR2QP_MASK ((uint)0x00000030) /* mask for IDMA2 req priority */
754 #define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */
755 #define RCCR_DR2QP_MED ((uint)0x00000010) /* IDMA2 has medium req priority */
756 #define RCCR_DR2QP_LOW ((uint)0x00000020) /* IDMA2 has low req priority */
757 #define RCCR_DR3QP_MASK ((uint)0x00000003) /* mask for IDMA3 req priority */
758 #define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */
759 #define RCCR_DR3QP_MED ((uint)0x00000001) /* IDMA3 has medium req priority */
760 #define RCCR_DR3QP_LOW ((uint)0x00000002) /* IDMA3 has low req priority */
761 #define RCCR_EIE ((uint)0x00080000) /* external interrupt enable */
762 #define RCCR_SCD ((uint)0x00040000) /* scheduler configuration */
763 #define RCCR_ERAM_MASK ((uint)0x0000e000) /* mask for enable RAM microcode */
764 #define RCCR_ERAM_0KB ((uint)0x00000000) /* use 0KB of dpram for microcode */
765 #define RCCR_ERAM_2KB ((uint)0x00002000) /* use 2KB of dpram for microcode */
766 #define RCCR_ERAM_4KB ((uint)0x00004000) /* use 4KB of dpram for microcode */
767 #define RCCR_ERAM_6KB ((uint)0x00006000) /* use 6KB of dpram for microcode */
768 #define RCCR_ERAM_8KB ((uint)0x00008000) /* use 8KB of dpram for microcode */
769 #define RCCR_ERAM_10KB ((uint)0x0000a000) /* use 10KB of dpram for microcode */
770 #define RCCR_ERAM_12KB ((uint)0x0000c000) /* use 12KB of dpram for microcode */
771 #define RCCR_EDM0 ((uint)0x00000800) /* DREQ0 edge detect mode */
772 #define RCCR_EDM1 ((uint)0x00000400) /* DREQ1 edge detect mode */
773 #define RCCR_EDM2 ((uint)0x00000200) /* DREQ2 edge detect mode */
774 #define RCCR_EDM3 ((uint)0x00000100) /* DREQ3 edge detect mode */
775 #define RCCR_DEM01 ((uint)0x00000008) /* DONE0/DONE1 edge detect mode */
776 #define RCCR_DEM23 ((uint)0x00000004) /* DONE2/DONE3 edge detect mode */
986 #define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */
993 #define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */
995 #define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
996 #define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
997 #define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
998 #define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
999 #define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
1000 #define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */
1005 #define CMX1_CLK_MASK ((uint)0xff000000)
1010 #define CMX2_CLK_MASK ((uint)0x00ff0000)
1015 #define CMX3_CLK_MASK ((uint)0x0000ff00)