Lines Matching refs:ushort
27 #define CPM_CR_RST ((ushort)0x8000)
28 #define CPM_CR_OPCODE ((ushort)0x0f00)
29 #define CPM_CR_CHAN ((ushort)0x00f0)
30 #define CPM_CR_FLG ((ushort)0x0001)
34 #define CPM_CR_CH_SCC1 ((ushort)0x0000)
35 #define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
36 #define CPM_CR_CH_SCC2 ((ushort)0x0004)
37 #define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */
39 #define CPM_CR_CH_SCC3 ((ushort)0x0008)
40 #define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
41 #define CPM_CR_CH_SCC4 ((ushort)0x000c)
42 #define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
77 ushort smc_rbase; /* Rx Buffer descriptor base address */
78 ushort smc_tbase; /* Tx Buffer descriptor base address */
81 ushort smc_mrblr; /* Max receive buffer length */
84 ushort smc_rbptr; /* Internal */
85 ushort smc_ibc; /* Internal */
89 ushort smc_tbptr; /* Internal */
90 ushort smc_tbc; /* Internal */
92 ushort smc_maxidl; /* Maximum idle characters */
93 ushort smc_tmpidl; /* Temporary idle counter */
94 ushort smc_brklen; /* Last received break length */
95 ushort smc_brkec; /* rcv'd break condition counter */
96 ushort smc_brkcr; /* xmt break count register */
97 ushort smc_rmask; /* Temporary bit mask */
99 ushort smc_rpbase; /* Relocation pointer */
108 #define SMCMR_REN ((ushort)0x0001)
109 #define SMCMR_TEN ((ushort)0x0002)
110 #define SMCMR_DM ((ushort)0x000c)
111 #define SMCMR_SM_GCI ((ushort)0x0000)
112 #define SMCMR_SM_UART ((ushort)0x0020)
113 #define SMCMR_SM_TRANS ((ushort)0x0030)
114 #define SMCMR_SM_MASK ((ushort)0x0030)
115 #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
117 #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
119 #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
120 #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
129 ushort scent_rbase;
130 ushort scent_tbase;
133 ushort scent_mrblr;
136 ushort scent_rbptr;
137 ushort scent_r_cnt;
141 ushort scent_tbptr;
142 ushort scent_t_cnt;
144 ushort scent_max_sl;
145 ushort scent_sl_cnt;
146 ushort scent_character1;
147 ushort scent_character2;
148 ushort scent_character3;
149 ushort scent_character4;
150 ushort scent_character5;
151 ushort scent_character6;
152 ushort scent_character7;
153 ushort scent_character8;
154 ushort scent_rccm;
155 ushort scent_rccr;
278 #define SCC_TODR_TOD ((ushort)0x8000)
288 ushort scc_rbase; /* Rx Buffer descriptor base address */
289 ushort scc_tbase; /* Tx Buffer descriptor base address */
292 ushort scc_mrblr; /* Max receive buffer length */
295 ushort scc_rbptr; /* Internal */
296 ushort scc_ibc; /* Internal */
300 ushort scc_tbptr; /* Internal */
301 ushort scc_tbc; /* Internal */
320 ushort sen_pads; /* Tx short frame pad character */
321 ushort sen_retlim; /* Retry limit threshold */
322 ushort sen_retcnt; /* Retry limit counter */
323 ushort sen_maxflr; /* maximum frame length register */
324 ushort sen_minflr; /* minimum frame length register */
325 ushort sen_maxd1; /* maximum DMA1 length */
326 ushort sen_maxd2; /* maximum DMA2 length */
327 ushort sen_maxd; /* Rx max DMA */
328 ushort sen_dmacnt; /* Rx DMA counter */
329 ushort sen_maxb; /* Max BD byte count */
330 ushort sen_gaddr1; /* Group address filter */
331 ushort sen_gaddr2;
332 ushort sen_gaddr3;
333 ushort sen_gaddr4;
338 ushort sen_tbuf0bcnt; /* Internal */
339 ushort sen_paddrh; /* physical address (MSB) */
340 ushort sen_paddrm;
341 ushort sen_paddrl; /* physical address (LSB) */
342 ushort sen_pper; /* persistence */
343 ushort sen_rfbdptr; /* Rx first BD pointer */
344 ushort sen_tfbdptr; /* Tx first BD pointer */
345 ushort sen_tlbdptr; /* Tx last BD pointer */
350 ushort sen_tbuf1bcnt; /* Internal */
351 ushort sen_txlen; /* Tx Frame length counter */
352 ushort sen_iaddr1; /* Individual address filter */
353 ushort sen_iaddr2;
354 ushort sen_iaddr3;
355 ushort sen_iaddr4;
356 ushort sen_boffcnt; /* Backoff counter */
361 ushort sen_taddrh; /* temp address (MSB) */
362 ushort sen_taddrm;
363 ushort sen_taddrl; /* temp address (LSB) */
368 #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
369 #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
370 #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
371 #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
372 #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
373 #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
377 #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
378 #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
379 #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
380 #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
381 #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
382 #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
383 #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
384 #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
385 #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
386 #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
387 #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
388 #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
389 #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
396 ushort scc_maxidl; /* Maximum idle chars */
397 ushort scc_idlc; /* temp idle counter */
398 ushort scc_brkcr; /* Break count register */
399 ushort scc_parec; /* receive parity error counter */
400 ushort scc_frmec; /* receive framing error counter */
401 ushort scc_nosec; /* receive noise counter */
402 ushort scc_brkec; /* receive break condition counter */
403 ushort scc_brkln; /* last received break length */
404 ushort scc_uaddr1; /* UART address character 1 */
405 ushort scc_uaddr2; /* UART address character 2 */
406 ushort scc_rtemp; /* Temp storage */
407 ushort scc_toseq; /* Transmit out of sequence char */
408 ushort scc_char1; /* control character 1 */
409 ushort scc_char2; /* control character 2 */
410 ushort scc_char3; /* control character 3 */
411 ushort scc_char4; /* control character 4 */
412 ushort scc_char5; /* control character 5 */
413 ushort scc_char6; /* control character 6 */
414 ushort scc_char7; /* control character 7 */
415 ushort scc_char8; /* control character 8 */
416 ushort scc_rccm; /* receive control character mask */
417 ushort scc_rccr; /* receive control character register */
418 ushort scc_rlbc; /* receive last break character */
423 #define UART_SCCM_GLR ((ushort)0x1000)
424 #define UART_SCCM_GLT ((ushort)0x0800)
425 #define UART_SCCM_AB ((ushort)0x0200)
426 #define UART_SCCM_IDL ((ushort)0x0100)
427 #define UART_SCCM_GRA ((ushort)0x0080)
428 #define UART_SCCM_BRKE ((ushort)0x0040)
429 #define UART_SCCM_BRKS ((ushort)0x0020)
430 #define UART_SCCM_CCR ((ushort)0x0008)
431 #define UART_SCCM_BSY ((ushort)0x0004)
432 #define UART_SCCM_TX ((ushort)0x0002)
433 #define UART_SCCM_RX ((ushort)0x0001)
437 #define SCU_PSMR_FLC ((ushort)0x8000)
438 #define SCU_PSMR_SL ((ushort)0x4000)
439 #define SCU_PSMR_CL ((ushort)0x3000)
440 #define SCU_PSMR_UM ((ushort)0x0c00)
441 #define SCU_PSMR_FRZ ((ushort)0x0200)
442 #define SCU_PSMR_RZS ((ushort)0x0100)
443 #define SCU_PSMR_SYN ((ushort)0x0080)
444 #define SCU_PSMR_DRT ((ushort)0x0040)
445 #define SCU_PSMR_PEN ((ushort)0x0010)
446 #define SCU_PSMR_RPM ((ushort)0x000c)
447 #define SCU_PSMR_REVP ((ushort)0x0008)
448 #define SCU_PSMR_TPM ((ushort)0x0003)
449 #define SCU_PSMR_TEVP ((ushort)0x0002)
462 ushort iic_rbase; /* Rx Buffer descriptor base address */
463 ushort iic_tbase; /* Tx Buffer descriptor base address */
466 ushort iic_mrblr; /* Max receive buffer length */
469 ushort iic_rbptr; /* Internal */
470 ushort iic_rbc; /* Internal */
474 ushort iic_tbptr; /* Internal */
475 ushort iic_tbc; /* Internal */
478 ushort iic_rpbase; /* Relocation pointer */
516 #define CPMVEC_PIO_PC15 ((ushort)0x1f)
517 #define CPMVEC_SCC1 ((ushort)0x1e)
518 #define CPMVEC_SCC2 ((ushort)0x1d)
519 #define CPMVEC_SCC3 ((ushort)0x1c)
520 #define CPMVEC_SCC4 ((ushort)0x1b)
521 #define CPMVEC_PIO_PC14 ((ushort)0x1a)
522 #define CPMVEC_TIMER1 ((ushort)0x19)
523 #define CPMVEC_PIO_PC13 ((ushort)0x18)
524 #define CPMVEC_PIO_PC12 ((ushort)0x17)
525 #define CPMVEC_SDMA_CB_ERR ((ushort)0x16)
526 #define CPMVEC_IDMA1 ((ushort)0x15)
527 #define CPMVEC_IDMA2 ((ushort)0x14)
528 #define CPMVEC_TIMER2 ((ushort)0x12)
529 #define CPMVEC_RISCTIMER ((ushort)0x11)
530 #define CPMVEC_I2C ((ushort)0x10)
531 #define CPMVEC_PIO_PC11 ((ushort)0x0f)
532 #define CPMVEC_PIO_PC10 ((ushort)0x0e)
533 #define CPMVEC_TIMER3 ((ushort)0x0c)
534 #define CPMVEC_PIO_PC9 ((ushort)0x0b)
535 #define CPMVEC_PIO_PC8 ((ushort)0x0a)
536 #define CPMVEC_PIO_PC7 ((ushort)0x09)
537 #define CPMVEC_TIMER4 ((ushort)0x07)
538 #define CPMVEC_PIO_PC6 ((ushort)0x06)
539 #define CPMVEC_SPI ((ushort)0x05)
540 #define CPMVEC_SMC1 ((ushort)0x04)
541 #define CPMVEC_SMC2 ((ushort)0x03)
542 #define CPMVEC_PIO_PC5 ((ushort)0x02)
543 #define CPMVEC_PIO_PC4 ((ushort)0x01)
544 #define CPMVEC_ERROR ((ushort)0x00)