Lines Matching refs:IO_STATE
52 IO_STATE(R_IRQ_MASK1_SET, ser0_data, set),
66 IO_STATE(R_IRQ_MASK1_SET, ser1_data, set),
80 IO_STATE(R_IRQ_MASK1_SET, ser2_data, set),
94 IO_STATE(R_IRQ_MASK1_SET, ser3_data, set),
148 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused); in start_port()
153 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb); in start_port()
158 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0); in start_port()
160 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, par0); in start_port()
161 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, ser2, select); in start_port()
166 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, par1); in start_port()
168 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, par1); in start_port()
169 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, ser3, select); in start_port()
175 IO_STATE(R_SERIAL0_XOFF, tx_stop, enable) | in start_port()
176 IO_STATE(R_SERIAL0_XOFF, auto_xoff, disable) | in start_port()
184 IO_STATE(R_SERIAL0_BAUD, tr_baud, c115k2Hz) | in start_port()
185 IO_STATE(R_SERIAL0_BAUD, rec_baud, c115k2Hz); in start_port()
189 IO_STATE(R_SERIAL0_BAUD, tr_baud, c1200Hz) | in start_port()
190 IO_STATE(R_SERIAL0_BAUD, rec_baud, c1200Hz); in start_port()
194 IO_STATE(R_SERIAL0_BAUD, tr_baud, c2400Hz) | in start_port()
195 IO_STATE(R_SERIAL0_BAUD, rec_baud, c2400Hz); in start_port()
199 IO_STATE(R_SERIAL0_BAUD, tr_baud, c4800Hz) | in start_port()
200 IO_STATE(R_SERIAL0_BAUD, rec_baud, c4800Hz); in start_port()
204 IO_STATE(R_SERIAL0_BAUD, tr_baud, c9600Hz) | in start_port()
205 IO_STATE(R_SERIAL0_BAUD, rec_baud, c9600Hz); in start_port()
209 IO_STATE(R_SERIAL0_BAUD, tr_baud, c19k2Hz) | in start_port()
210 IO_STATE(R_SERIAL0_BAUD, rec_baud, c19k2Hz); in start_port()
214 IO_STATE(R_SERIAL0_BAUD, tr_baud, c38k4Hz) | in start_port()
215 IO_STATE(R_SERIAL0_BAUD, rec_baud, c38k4Hz); in start_port()
219 IO_STATE(R_SERIAL0_BAUD, tr_baud, c57k6Hz) | in start_port()
220 IO_STATE(R_SERIAL0_BAUD, rec_baud, c57k6Hz); in start_port()
224 IO_STATE(R_SERIAL0_BAUD, tr_baud, c115k2Hz) | in start_port()
225 IO_STATE(R_SERIAL0_BAUD, rec_baud, c115k2Hz); in start_port()
231 IO_STATE(R_SERIAL0_REC_CTRL, rec_par, even) | in start_port()
232 IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable); in start_port()
234 IO_STATE(R_SERIAL0_TR_CTRL, tr_par, even) | in start_port()
235 IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable); in start_port()
238 IO_STATE(R_SERIAL0_REC_CTRL, rec_par, odd) | in start_port()
239 IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable); in start_port()
241 IO_STATE(R_SERIAL0_TR_CTRL, tr_par, odd) | in start_port()
242 IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable); in start_port()
245 IO_STATE(R_SERIAL0_REC_CTRL, rec_par, even) | in start_port()
246 IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, disable); in start_port()
248 IO_STATE(R_SERIAL0_TR_CTRL, tr_par, even) | in start_port()
249 IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, disable); in start_port()
253 rec_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_7bit); in start_port()
254 tr_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_7bit); in start_port()
258 rec_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_8bit); in start_port()
259 tr_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_8bit); in start_port()
263 IO_STATE(R_SERIAL0_REC_CTRL, dma_err, stop) | in start_port()
264 IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable) | in start_port()
265 IO_STATE(R_SERIAL0_REC_CTRL, rts_, active) | in start_port()
266 IO_STATE(R_SERIAL0_REC_CTRL, sampling, middle) | in start_port()
267 IO_STATE(R_SERIAL0_REC_CTRL, rec_stick_par, normal) | in start_port()
272 IO_STATE(R_SERIAL0_TR_CTRL, tr_enable, enable) | in start_port()
273 IO_STATE(R_SERIAL0_TR_CTRL, auto_cts, disabled) | in start_port()
274 IO_STATE(R_SERIAL0_TR_CTRL, stop_bits, one_bit) | in start_port()
275 IO_STATE(R_SERIAL0_TR_CTRL, tr_stick_par, normal) | in start_port()
380 *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, serial, set); in enableDebugIRQ()
382 *kgdb_port->rec_ctrl = IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable); in enableDebugIRQ()