Lines Matching refs:config
510 struct pll_clk_config *config = clk->private_data; in pll_clk_recalc() local
513 mode = (readl(config->mode_reg) >> config->masks->mode_shift) & in pll_clk_recalc()
514 config->masks->mode_mask; in pll_clk_recalc()
516 val = readl(config->cfg_reg); in pll_clk_recalc()
518 den = (val >> config->masks->div_p_shift) & config->masks->div_p_mask; in pll_clk_recalc()
520 den *= (val >> config->masks->div_n_shift) & config->masks->div_n_mask; in pll_clk_recalc()
525 num *= (val >> config->masks->norm_fdbk_m_shift) & in pll_clk_recalc()
526 config->masks->norm_fdbk_m_mask; in pll_clk_recalc()
529 num *= (val >> config->masks->dith_fdbk_m_shift) & in pll_clk_recalc()
530 config->masks->dith_fdbk_m_mask; in pll_clk_recalc()
547 struct pll_clk_config *config = clk->private_data; in pll_clk_set_rate() local
555 val = readl(config->mode_reg) & in pll_clk_set_rate()
556 ~(config->masks->mode_mask << config->masks->mode_shift); in pll_clk_set_rate()
557 val |= (tbls[i].mode & config->masks->mode_mask) << in pll_clk_set_rate()
558 config->masks->mode_shift; in pll_clk_set_rate()
559 writel(val, config->mode_reg); in pll_clk_set_rate()
561 val = readl(config->cfg_reg) & in pll_clk_set_rate()
562 ~(config->masks->div_p_mask << config->masks->div_p_shift); in pll_clk_set_rate()
563 val |= (tbls[i].p & config->masks->div_p_mask) << in pll_clk_set_rate()
564 config->masks->div_p_shift; in pll_clk_set_rate()
565 val &= ~(config->masks->div_n_mask << config->masks->div_n_shift); in pll_clk_set_rate()
566 val |= (tbls[i].n & config->masks->div_n_mask) << in pll_clk_set_rate()
567 config->masks->div_n_shift; in pll_clk_set_rate()
568 val &= ~(config->masks->dith_fdbk_m_mask << in pll_clk_set_rate()
569 config->masks->dith_fdbk_m_shift); in pll_clk_set_rate()
571 val |= (tbls[i].m & config->masks->dith_fdbk_m_mask) << in pll_clk_set_rate()
572 config->masks->dith_fdbk_m_shift; in pll_clk_set_rate()
574 val |= (tbls[i].m & config->masks->norm_fdbk_m_mask) << in pll_clk_set_rate()
575 config->masks->norm_fdbk_m_shift; in pll_clk_set_rate()
577 writel(val, config->cfg_reg); in pll_clk_set_rate()
598 struct bus_clk_config *config = clk->private_data; in bus_clk_recalc() local
601 div = ((readl(config->reg) >> config->masks->shift) & in bus_clk_recalc()
602 config->masks->mask) + 1; in bus_clk_recalc()
615 struct bus_clk_config *config = clk->private_data; in bus_clk_set_rate() local
623 val = readl(config->reg) & in bus_clk_set_rate()
624 ~(config->masks->mask << config->masks->shift); in bus_clk_set_rate()
625 val |= (tbls[i].div & config->masks->mask) << config->masks->shift; in bus_clk_set_rate()
626 writel(val, config->reg); in bus_clk_set_rate()
662 struct aux_clk_config *config = clk->private_data; in aux_clk_recalc() local
665 val = readl(config->synth_reg); in aux_clk_recalc()
667 eqn = (val >> config->masks->eq_sel_shift) & in aux_clk_recalc()
668 config->masks->eq_sel_mask; in aux_clk_recalc()
669 if (eqn == config->masks->eq1_mask) in aux_clk_recalc()
673 num = (val >> config->masks->xscale_sel_shift) & in aux_clk_recalc()
674 config->masks->xscale_sel_mask; in aux_clk_recalc()
677 den *= (val >> config->masks->yscale_sel_shift) & in aux_clk_recalc()
678 config->masks->yscale_sel_mask; in aux_clk_recalc()
691 struct aux_clk_config *config = clk->private_data; in aux_clk_set_rate() local
699 val = readl(config->synth_reg) & in aux_clk_set_rate()
700 ~(config->masks->eq_sel_mask << config->masks->eq_sel_shift); in aux_clk_set_rate()
701 val |= (tbls[i].eq & config->masks->eq_sel_mask) << in aux_clk_set_rate()
702 config->masks->eq_sel_shift; in aux_clk_set_rate()
703 val &= ~(config->masks->xscale_sel_mask << in aux_clk_set_rate()
704 config->masks->xscale_sel_shift); in aux_clk_set_rate()
705 val |= (tbls[i].xscale & config->masks->xscale_sel_mask) << in aux_clk_set_rate()
706 config->masks->xscale_sel_shift; in aux_clk_set_rate()
707 val &= ~(config->masks->yscale_sel_mask << in aux_clk_set_rate()
708 config->masks->yscale_sel_shift); in aux_clk_set_rate()
709 val |= (tbls[i].yscale & config->masks->yscale_sel_mask) << in aux_clk_set_rate()
710 config->masks->yscale_sel_shift; in aux_clk_set_rate()
711 writel(val, config->synth_reg); in aux_clk_set_rate()
739 struct gpt_clk_config *config = clk->private_data; in gpt_clk_recalc() local
742 val = readl(config->synth_reg); in gpt_clk_recalc()
743 div += (val >> config->masks->mscale_sel_shift) & in gpt_clk_recalc()
744 config->masks->mscale_sel_mask; in gpt_clk_recalc()
745 div *= 1 << (((val >> config->masks->nscale_sel_shift) & in gpt_clk_recalc()
746 config->masks->nscale_sel_mask) + 1); in gpt_clk_recalc()
759 struct gpt_clk_config *config = clk->private_data; in gpt_clk_set_rate() local
767 val = readl(config->synth_reg) & ~(config->masks->mscale_sel_mask << in gpt_clk_set_rate()
768 config->masks->mscale_sel_shift); in gpt_clk_set_rate()
769 val |= (tbls[i].mscale & config->masks->mscale_sel_mask) << in gpt_clk_set_rate()
770 config->masks->mscale_sel_shift; in gpt_clk_set_rate()
771 val &= ~(config->masks->nscale_sel_mask << in gpt_clk_set_rate()
772 config->masks->nscale_sel_shift); in gpt_clk_set_rate()
773 val |= (tbls[i].nscale & config->masks->nscale_sel_mask) << in gpt_clk_set_rate()
774 config->masks->nscale_sel_shift; in gpt_clk_set_rate()
775 writel(val, config->synth_reg); in gpt_clk_set_rate()
821 struct clcd_clk_config *config = clk->private_data; in clcd_clk_recalc() local
826 val = readl(config->synth_reg); in clcd_clk_recalc()
827 div = (val >> config->masks->div_factor_shift) & in clcd_clk_recalc()
828 config->masks->div_factor_mask; in clcd_clk_recalc()
844 struct clcd_clk_config *config = clk->private_data; in clcd_clk_set_rate() local
852 val = readl(config->synth_reg) & ~(config->masks->div_factor_mask << in clcd_clk_set_rate()
853 config->masks->div_factor_shift); in clcd_clk_set_rate()
854 val |= (tbls[i].div & config->masks->div_factor_mask) << in clcd_clk_set_rate()
855 config->masks->div_factor_shift; in clcd_clk_set_rate()
856 writel(val, config->synth_reg); in clcd_clk_set_rate()