Lines Matching refs:r0
47 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
48 bic r0, r0, #0x00001000 @ i-cache
49 bic r0, r0, #0x00000004 @ d-cache
50 mcr p15, 0, r0, c1, c0, 0 @ disable caches
68 mov pc, r0
77 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
86 mov r0, #0
87 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
135 sub r3, r1, r0 @ calculate total size
141 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
142 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
143 add r0, r0, #CACHE_DLINESIZE
144 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
146 add r0, r0, #CACHE_DLINESIZE
148 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
149 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
150 add r0, r0, #CACHE_DLINESIZE
151 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
152 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
153 add r0, r0, #CACHE_DLINESIZE
155 cmp r0, r1
186 bic r0, r0, #CACHE_DLINESIZE - 1
187 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
188 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
189 add r0, r0, #CACHE_DLINESIZE
190 cmp r0, r1
192 mcr p15, 0, r0, c7, c10, 4 @ drain WB
206 add r1, r0, r1
207 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
208 add r0, r0, #CACHE_DLINESIZE
209 cmp r0, r1
211 mov r0, #0
212 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
213 mcr p15, 0, r0, c7, c10, 4 @ drain WB
230 tst r0, #CACHE_DLINESIZE - 1
231 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
235 bic r0, r0, #CACHE_DLINESIZE - 1
236 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
237 add r0, r0, #CACHE_DLINESIZE
238 cmp r0, r1
240 mcr p15, 0, r0, c7, c10, 4 @ drain WB
255 bic r0, r0, #CACHE_DLINESIZE - 1
256 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
257 add r0, r0, #CACHE_DLINESIZE
258 cmp r0, r1
261 mcr p15, 0, r0, c7, c10, 4 @ drain WB
275 bic r0, r0, #CACHE_DLINESIZE - 1
278 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
280 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
282 add r0, r0, #CACHE_DLINESIZE
283 cmp r0, r1
285 mcr p15, 0, r0, c7, c10, 4 @ drain WB
295 add r1, r1, r0
317 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
318 add r0, r0, #CACHE_DLINESIZE
322 mcr p15, 0, r0, c7, c10, 4 @ drain WB
329 mov r0, #0
330 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
331 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
332 mcr p15, 0, r0, c7, c10, 4 @ drain WB
334 mcr p15, 0, r0, c6, c3, 0 @ disable memory region 3~7
335 mcr p15, 0, r0, c6, c4, 0
336 mcr p15, 0, r0, c6, c5, 0
337 mcr p15, 0, r0, c6, c6, 0
338 mcr p15, 0, r0, c6, c7, 0
340 mov r0, #0x0000003F @ base = 0, size = 4GB
341 mcr p15, 0, r0, c6, c0, 0 @ set region 0, default
343 ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
349 orr r0, r0, r2, lsl #1 @ the region register value
350 orr r0, r0, #1 @ set enable bit
351 mcr p15, 0, r0, c6, c1, 0 @ set region 1, RAM
353 ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
359 orr r0, r0, r2, lsl #1 @ the region register value
360 orr r0, r0, #1 @ set enable bit
361 mcr p15, 0, r0, c6, c2, 0 @ set region 2, ROM/FLASH
363 mov r0, #0x06
364 mcr p15, 0, r0, c2, c0, 0 @ region 1,2 d-cacheable
365 mcr p15, 0, r0, c2, c0, 1 @ region 1,2 i-cacheable
367 mov r0, #0x00 @ disable whole write buffer
369 mov r0, #0x02 @ region 1 write bufferred
371 mcr p15, 0, r0, c3, c0, 0
382 mov r0, #0x00000031
383 orr r0, r0, #0x00000200
384 mcr p15, 0, r0, c5, c0, 2 @ set data access permission
385 mcr p15, 0, r0, c5, c0, 3 @ set inst. access permission
387 mrc p15, 0, r0, c1, c0 @ get control register
388 orr r0, r0, #0x00001000 @ I-cache
389 orr r0, r0, #0x00000005 @ MPU/D-cache
391 orr r0, r0, #0x00004000 @ .1.. .... .... ....