Lines Matching refs:r0
64 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
65 bic r0, r0, #0x1000 @ ...i............
66 bic r0, r0, #0x000e @ ............wca.
67 mcr p15, 0, r0, c1, c0, 0 @ disable caches
92 mov pc, r0
103 mov r0, #0
105 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
111 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
122 mov r0, #0
123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
168 sub r3, r1, r0 @ calculate total size
173 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
174 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
175 add r0, r0, #CACHE_DLINESIZE
176 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
177 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
178 add r0, r0, #CACHE_DLINESIZE
180 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
181 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
182 add r0, r0, #CACHE_DLINESIZE
183 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
184 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
185 add r0, r0, #CACHE_DLINESIZE
187 cmp r0, r1
217 bic r0, r0, #CACHE_DLINESIZE - 1
218 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
219 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
220 add r0, r0, #CACHE_DLINESIZE
221 cmp r0, r1
223 mcr p15, 0, r0, c7, c10, 4 @ drain WB
236 add r1, r0, r1
237 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
238 add r0, r0, #CACHE_DLINESIZE
239 cmp r0, r1
241 mov r0, #0
242 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
243 mcr p15, 0, r0, c7, c10, 4 @ drain WB
261 tst r0, #CACHE_DLINESIZE - 1
262 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
266 bic r0, r0, #CACHE_DLINESIZE - 1
267 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
268 add r0, r0, #CACHE_DLINESIZE
269 cmp r0, r1
271 mcr p15, 0, r0, c7, c10, 4 @ drain WB
286 bic r0, r0, #CACHE_DLINESIZE - 1
287 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
288 add r0, r0, #CACHE_DLINESIZE
289 cmp r0, r1
292 mcr p15, 0, r0, c7, c10, 4 @ drain WB
304 bic r0, r0, #CACHE_DLINESIZE - 1
307 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
309 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
311 add r0, r0, #CACHE_DLINESIZE
312 cmp r0, r1
314 mcr p15, 0, r0, c7, c10, 4 @ drain WB
324 add r1, r1, r0
346 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
347 add r0, r0, #CACHE_DLINESIZE
351 mcr p15, 0, r0, c7, c10, 4 @ drain WB
376 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
390 mov r0, r0
392 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
394 mcr p15, 0, r0, c7, c10, 4 @ drain WB
407 stmia r0, {r4 - r6}
415 ldmia r0, {r4 - r6}
419 mov r0, r6 @ control register
428 mov r0, #0
429 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
430 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
432 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
437 mov r0, #4 @ disable write-back on caches explicitly
438 mcr p15, 7, r0, c15, c0, 0
443 mrc p15, 0, r0, c1, c0 @ get control register v4
444 bic r0, r0, r5
445 orr r0, r0, r6
447 orr r0, r0, #0x4000 @ .1.. .... .... ....