Lines Matching refs:readw
126 val = readw(clk->res_reg); in syscon_block_reset_enable()
142 val = readw(clk->res_reg); in syscon_block_reset_disable()
157 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMCR); in __clk_get()
165 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMCR); in __clk_get()
213 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); in syscon_clk_get_rate()
227 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); in enable_i2s0_vcxo()
232 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR); in enable_i2s0_vcxo()
245 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); in enable_i2s1_vcxo()
250 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR); in enable_i2s1_vcxo()
263 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); in disable_i2s0_vcxo()
270 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR); in disable_i2s0_vcxo()
283 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); in disable_i2s1_vcxo()
290 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR); in disable_i2s1_vcxo()
339 reg = readw(U300_SYSCON_VBASE + U300_SYSCON_MMF0R) & in syscon_clk_rate_set_mclk()
367 val |= readw(U300_SYSCON_VBASE + U300_SYSCON_CCR) & in syscon_clk_rate_set_cpuclk()
549 u16 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMF0R) & in clk_get_rate_mclk()
1472 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); in u300_clock_init()
1476 while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) & in u300_clock_init()
1480 val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMCR); in u300_clock_init()