Lines Matching refs:U300_SYSCON_CCR
213 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); in syscon_clk_get_rate()
227 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); in enable_i2s0_vcxo()
229 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); in enable_i2s0_vcxo()
231 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); in enable_i2s0_vcxo()
245 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); in enable_i2s1_vcxo()
247 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); in enable_i2s1_vcxo()
249 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); in enable_i2s1_vcxo()
263 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); in disable_i2s0_vcxo()
265 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); in disable_i2s0_vcxo()
269 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); in disable_i2s0_vcxo()
283 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); in disable_i2s1_vcxo()
285 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); in disable_i2s1_vcxo()
289 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); in disable_i2s1_vcxo()
367 val |= readw(U300_SYSCON_VBASE + U300_SYSCON_CCR) & in syscon_clk_rate_set_cpuclk()
369 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); in syscon_clk_rate_set_cpuclk()
1472 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); in u300_clock_init()
1474 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); in u300_clock_init()