Lines Matching refs:mul
566 c->mul = 1; in tegra30_pll_ref_init()
610 c->mul = 2; in tegra30_super_clk_init()
667 c->mul = 2; in tegra30_super_clk_set_parent()
704 c->mul = 2; in tegra30_super_clk_set_rate()
721 c->rate = (rate * c->mul) / c->div; in tegra30_twd_clk_set_rate()
737 c->mul = 1; in tegra30_blink_clk_init()
901 c->mul = sel->n; in tegra30_pll_clk_init()
909 c->mul = 1; in tegra30_pll_clk_init()
912 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; in tegra30_pll_clk_init()
1064 c->mul = sel->n; in tegra30_pll_clk_set_rate()
1163 c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT; in tegra30_plle_clk_init()
1233 c->mul = sel->n; in tegra30_plle_configure()
1280 c->mul = 2; in tegra30_pll_div_clk_init()
1285 c->mul = 1; in tegra30_pll_div_clk_init()
1291 c->mul = 1; in tegra30_pll_div_clk_init()
1361 c->mul = 2; in tegra30_pll_div_clk_set_rate()
1458 c->mul = 2; in tegra30_periph_clk_init()
1462 c->mul = 1; in tegra30_periph_clk_init()
1465 c->mul = 1; in tegra30_periph_clk_init()
1592 c->mul = 2; in tegra30_periph_clk_set_rate()
1603 c->mul = 1; in tegra30_periph_clk_set_rate()
1608 c->mul = 1; in tegra30_periph_clk_set_rate()
1782 c->mul = 1; in tegra30_clk_out_init()
1866 c->mul = val & (0x1 << c->reg_shift) ? 1 : 2; in tegra30_clk_double_init()
1880 c->mul = 1; in tegra30_clk_double_set_rate()
1886 c->mul = 2; in tegra30_clk_double_set_rate()
2020 .mul = 1,
2030 .mul = 1,
2819 .mul = 1,