Lines Matching refs:r0
22 ldr r0, =PSSR
31 str r1, [r0] @ make sure PSSR_PH/STS are clear
64 mcr p14, 0, r0, c7, c0, 0
69 ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN
70 bic r0, r0, #PXA3_DDR_HCAL_HCEN
71 str r0, [r1, #PXA3_DDR_HCAL]
72 1: ldr r0, [r1, #PXA3_DDR_HCAL]
73 tst r0, #PXA3_DDR_HCAL_HCEN
76 ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP
77 orr r0, r0, #PXA3_RCOMP_SWEVAL
78 str r0, [r1, #PXA3_RCOMP]
80 mov r0, #~0 @ Clear interrupts
81 str r0, [r1, #PXA3_DMCISR]
83 ldr r0, [r1, #PXA3_DMCIER] @ set DMIER[EDLP]
84 orr r0, r0, #PXA3_DMCIER_EDLP
85 str r0, [r1, #PXA3_DMCIER]
87 ldr r0, [r1, #PXA3_DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN
88 bic r0, r0, #PXA3_DDR_HCAL_HCRNG
89 orr r0, r0, #PXA3_DDR_HCAL_HCEN | PXA3_DDR_HCAL_HCPROG
90 str r0, [r1, #PXA3_DDR_HCAL]
92 1: ldr r0, [r1, #PXA3_DMCISR]
93 tst r0, #PXA3_DMCIER_EDLP
96 ldr r0, [r1, #PXA3_MDCNFG] @ set PXA3_MDCNFG[DMCEN]
97 orr r0, r0, #PXA3_MDCNFG_DMCEN
98 str r0, [r1, #PXA3_MDCNFG]
99 1: ldr r0, [r1, #PXA3_MDCNFG]
100 tst r0, #PXA3_MDCNFG_DMCEN
103 ldr r0, [r1, #PXA3_DDR_HCAL] @ set PXA3_DDR_HCAL[HCRNG]
104 orr r0, r0, #2 @ HCRNG
105 str r0, [r1, #PXA3_DDR_HCAL]
107 ldr r0, [r1, #PXA3_DMCIER] @ Clear the interrupt
108 bic r0, r0, #0x20000000
109 str r0, [r1, #PXA3_DMCIER]