Lines Matching refs:__REG
10 #define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
11 #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
12 #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
13 #define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
14 #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
15 #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
16 #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
17 #define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
18 #define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
19 #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
20 #define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
21 #define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
22 #define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
26 #define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */
27 #define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
28 #define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */
29 #define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */
30 #define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */
31 #define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */
32 #define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */
33 #define BTLSR __REG(0x40200014) /* Line Status Register (read only) */
34 #define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */
35 #define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */
36 #define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */
37 #define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
38 #define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
42 #define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */
43 #define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */
44 #define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */
45 #define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */
46 #define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */
47 #define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */
48 #define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */
49 #define STLSR __REG(0x40700014) /* Line Status Register (read only) */
50 #define STMSR __REG(0x40700018) /* Reserved */
51 #define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */
52 #define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */
53 #define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
54 #define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
58 #define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */
59 #define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */
60 #define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */
61 #define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */
62 #define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */
63 #define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */
64 #define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */
65 #define HWLSR __REG(0x41600014) /* Line Status Register (read only) */
66 #define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */
67 #define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */
68 #define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */
69 #define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */
70 #define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */
71 #define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */
72 #define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
73 #define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */