117 		return clk_get_rate(&ckih_clk);  in pll_ref_get_rate()
145 		return clk_get_rate(&ckih_clk);  in mcu_pll_get_rate()
207 		return clk_get_rate(&serial_pll_clk);  in mcu_main_get_rate()
209 		return clk_get_rate(&mcu_pll_clk);  in mcu_main_get_rate()
218 	return clk_get_rate(clk->parent) / (max_pdf + 1);  in ahb_get_rate()
227 	return clk_get_rate(clk->parent) / (ipg_pdf + 1);  in ipg_get_rate()
236 	return clk_get_rate(clk->parent) / (nfc_pdf + 1);  in nfc_get_rate()
245 	return clk_get_rate(clk->parent) / (hsp_pdf + 1);  in hsp_get_rate()
256 	return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1);  in usb_get_rate()
270 	return clk_get_rate(clk->parent) / (pre * post);  in csi_get_rate()
275 	u32 pre, post, parent = clk_get_rate(clk->parent);  in csi_round_rate()
288 	u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);  in csi_set_rate()
315 	return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1);  in ssi1_get_rate()
326 	return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1);  in ssi2_get_rate()
337 	return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1);  in firi_get_rate()
343 	u32 parent = clk_get_rate(clk->parent);  in firi_round_rate()
357 	u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);  in firi_set_rate()
378 	return clk_get_rate(clk->parent) / 2;  in mbx_get_rate()
387 	return clk_get_rate(clk->parent) / (msti_pdf + 1);  in mstick1_get_rate()
396 	return clk_get_rate(clk->parent) / (msti_pdf + 1);  in mstick2_get_rate()
609 	pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk));  in mx31_clocks_init()