Lines Matching refs:exynos4_vpll_div
1373 static u32 exynos4_vpll_div[][8] = { variable
1403 for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) { in exynos4_vpll_set_rate()
1404 if (exynos4_vpll_div[i][0] == rate) { in exynos4_vpll_set_rate()
1405 vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT; in exynos4_vpll_set_rate()
1406 vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT; in exynos4_vpll_set_rate()
1407 vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT; in exynos4_vpll_set_rate()
1408 vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT; in exynos4_vpll_set_rate()
1409 vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT; in exynos4_vpll_set_rate()
1410 vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT; in exynos4_vpll_set_rate()
1411 vpll_con0 |= exynos4_vpll_div[i][7] << 27; in exynos4_vpll_set_rate()
1416 if (i == ARRAY_SIZE(exynos4_vpll_div)) { in exynos4_vpll_set_rate()