Lines Matching refs:PCI

3                       PCI Bus EEH Error Recovery
12 The IBM POWER-based pSeries and iSeries computers include PCI bus
14 reporting a large variety of PCI bus error conditions.  These features
16 hardware features allow PCI bus errors to be cleared and a PCI
20 This is in contrast to traditional PCI error handling, where the
21 PCI chip is wired directly to the CPU, and an error would cause
27 reliable and robust by protecting it from PCI errors, and giving
28 the OS the ability to "reboot"/recover individual PCI devices.
30 Future systems from other vendors, based on the PCI-E specification,
37 as PCI cards dying from heat, humidity, dust, vibration and bad
39 "real life" are due to either poorly seated PCI cards, or,
41 bugs, and sometimes PCI card hardware bugs.
51 connectivity due to a poorly seated card), and PCI-X split-completion
52 errors (due to software, device firmware, or device PCI hardware bugs).
54 physically removing and re-seating the PCI card.
67 When a PCI Host Bridge (PHB, the bus controller connecting the
68 PCI bus to the system CPU electronics complex) detects a PCI error
69 condition, it will "isolate" the affected PCI card.  Isolation
75 This includes access to PCI memory, I/O space, and PCI config
82 the EEH function in the PCI chipsets directly, primarily because
88 If the OS or device driver suspects that a PCI slot has been
93 would consist of resetting the PCI device (holding the PCI #RST
100 do not need to know that the PCI card has been "rebooted" in this
108 syslogd (/var/log/messages) to alert the sysadmin of PCI resets.
110 PCI hotplug tools to remove and replace the dead card.
117 EEH recovery.  This generic mechanism piggy-backs on the PCI hotplug
123 and if a PCI slot is hot-plugged. The former is performed by
126 EEH must be enabled before a PCI scan of the device can proceed.
129 EEH can no longer be turned off.  PCI devices *must* be
131 the I/O address ranges of the PCI device in order to detect an
143 all of these occur during boot, when the PCI bus is scanned, where
165 rtas_set_slot_reset() -- assert the  PCI #RST line for 1/8th of a second
166 rtas_configure_bridge() -- ask firmware to configure any PCI bridges
168 eeh_save_bars() and eeh_restore_bars(): save and restore the PCI
180 It then resets the PCI card, reconfigures the device BAR's, and