Lines Matching refs:stores

142 Furthermore, the stores committed by a CPU to the memory system may not be
143 perceived by the loads made by another CPU in the same order as the stores were
205  (*) Overlapping loads and stores within a particular CPU will appear to be
222      (Loads and stores overlap if they are targeted at overlapping pieces of
227  (*) It _must_not_ be assumed that independent loads and stores will be issued
294      A write barrier is a partial ordering on stores only; it is not required
298      memory system as time progresses.  All stores before a write barrier will
299      occur in the sequence _before_ all the stores after the write barrier.
315      only; it is not required to have any effect on stores, independent loads
319      committing sequences of stores to the memory system that the CPU being
322      load touches one of a sequence of stores from another CPU, then by the
323      time the barrier completes, the effects of all the stores prior to that
349      have any effect on stores.
365      A general memory barrier is a partial ordering over both loads and stores.
582 [!] Note that the stores before the write barrier would normally be expected to
624 	|       |       +------+     }        requires all stores prior to the
626 	|       |  :    +------+     }        further stores may take place
631 	                   | Sequence in which stores are committed to the
1375 order multiple stores before the wake-up with respect to loads of those stored
1530 this will ensure that the two stores issued on CPU 1 appear at the PCI bridge
1531 before either of the stores issued on CPU 2.
1780  (1) On some systems, I/O stores are not strongly ordered across all CPUs, and
1890      force stores to be ordered.
1991 their own loads and stores as if they had happened in program order.
2193      execution progress, whereas stores can often be deferred without a
2205  (*) loads and stores may be combined to improve performance when talking to