Lines Matching refs:BIT
54 #define HCC_LEN BIT(17) /* Link power management (LPM) capability */
60 #define HOSTCAP BIT(8) /* host capable */
61 #define DEVCAP BIT(7) /* device capable */
71 #define EXTS_TI1 BIT(4) /* general purpose timer interrupt 1 */
72 #define EXTS_TI1TI0 BIT(3) /* general purpose timer interrupt 0 */
73 #define EXTS_TI1UPI BIT(2) /* USB host periodic interrupt */
74 #define EXTS_TI1UAI BIT(1) /* USB host asynchronous interrupt */
75 #define EXTS_TI1NAKI BIT(0) /* NAK interrupt */
77 #define EXTI_TIE1 BIT(4) /* general purpose timer interrupt enable 1 */
78 #define EXTI_TIE0 BIT(3) /* general purpose timer interrupt enable 0 */
79 #define EXTI_UPIE BIT(2) /* USB host periodic interrupt enable */
80 #define EXTI_UAIE BIT(1) /* USB host asynchronous interrupt enable */
81 #define EXTI_NAKE BIT(0) /* NAK interrupt enable */
88 #define CMD_PPE BIT(15) /* per-port change events enable */
89 #define CMD_ATDTW BIT(14) /* add dTD tripwire */
90 #define CMD_SUTW BIT(13) /* setup tripwire */
91 #define CMD_ASPE BIT(11) /* asynchronous schedule park mode enable */
92 #define CMD_FS2 BIT(10) /* frame list size */
93 #define CMD_ASP1 BIT(9) /* asynchronous schedule park mode count */
94 #define CMD_ASP0 BIT(8)
95 #define CMD_LR BIT(7) /* light host/device controller reset */
96 #define CMD_IAA BIT(6) /* interrupt on async advance doorbell */
97 #define CMD_ASE BIT(5) /* asynchronous schedule enable */
98 #define CMD_PSE BIT(4) /* periodic schedule enable */
99 #define CMD_FS1 BIT(3)
100 #define CMD_FS0 BIT(2)
101 #define CMD_RST BIT(1) /* controller reset */
102 #define CMD_RUNSTOP BIT(0) /* run/stop */
106 #define STS_AS BIT(15) /* asynchronous schedule status */
107 #define STS_PS BIT(14) /* periodic schedule status */
108 #define STS_RCL BIT(13) /* reclamation */
109 #define STS_HCH BIT(12) /* HC halted */
110 #define STS_ULPII BIT(10) /* ULPI interrupt */
111 #define STS_SLI BIT(8) /* DC suspend */
112 #define STS_SRI BIT(7) /* SOF received */
113 #define STS_URI BIT(6) /* USB reset received */
114 #define STS_AAI BIT(5) /* interrupt on async advance */
115 #define STS_SEI BIT(4) /* system error */
116 #define STS_FRI BIT(3) /* frame list rollover */
117 #define STS_PCI BIT(2) /* port change detect */
118 #define STS_UEI BIT(1) /* USB error interrupt */
119 #define STS_UI BIT(0) /* USB interrupt */
123 #define INTR_ULPIE BIT(10) /* ULPI enable */
124 #define INTR_SLE BIT(8) /* DC sleep/suspend enable */
125 #define INTR_SRE BIT(7) /* SOF received enable */
126 #define INTR_URE BIT(6) /* USB reset enable */
127 #define INTR_AAE BIT(5) /* interrupt on async advance enable */
128 #define INTR_SEE BIT(4) /* system error enable */
129 #define INTR_FRE BIT(3) /* frame list rollover enable */
130 #define INTR_PCE BIT(2) /* port change detect enable */
131 #define INTR_UEE BIT(1) /* USB error interrupt enable */
132 #define INTR_UE BIT(0) /* USB interrupt enable */
141 #define USBADRA BIT(24) /* device address advance */
158 #define ULPIWU BIT(31) /* ULPI wakeup */
159 #define ULPIRUN BIT(30) /* ULPI read/write run */
160 #define ULPIRW BIT(29) /* ULPI read/write control */
161 #define ULPISS BIT(27) /* ULPI sync state */
176 #define PORTS_SSTS (BIT(24) | BIT(23)) /* suspend status */
177 #define PORTS_WKOC BIT(22) /* wake on over-current enable */
178 #define PORTS_WKDS BIT(21) /* wake on disconnect enable */
179 #define PORTS_WKCN BIT(20) /* wake on connect enable */
181 #define PORTS_PIC (BIT(15) | BIT(14)) /* port indicator control */
182 #define PORTS_PO BIT(13) /* port owner */
183 #define PORTS_PP BIT(12) /* port power */
184 #define PORTS_LS (BIT(11) | BIT(10)) /* line status */
185 #define PORTS_SLP BIT(9) /* suspend using L1 */
186 #define PORTS_PR BIT(8) /* port reset */
187 #define PORTS_SUSP BIT(7) /* suspend */
188 #define PORTS_FPR BIT(6) /* force port resume */
189 #define PORTS_OCC BIT(5) /* over-current change */
190 #define PORTS_OCA BIT(4) /* over-current active */
191 #define PORTS_PEC BIT(3) /* port enable/disable change */
192 #define PORTS_PE BIT(2) /* port enable/disable */
193 #define PORTS_CSC BIT(1) /* connect status change */
194 #define PORTS_CCS BIT(0) /* current connect status */
200 #define LPM_STS BIT(28) /* serial transceiver select */
201 #define LPM_PTW BIT(27) /* parallel transceiver width */
203 #define LPM_PSPD_MASK (BIT(26) | BIT(25))
207 #define LPM_SRT BIT(24) /* shorten reset time */
208 #define LPM_PFSC BIT(23) /* port force full speed connect */
209 #define LPM_PHCD BIT(22) /* PHY low power suspend clock disable */
210 #define LPM_STL BIT(16) /* STALL reply to LPM token */
213 #define LPM_NYT_ACK BIT(0) /* NYET/ACK reply to LPM token */
217 #define OTGSC_DPIE BIT(30) /* data pulse interrupt enable */
218 #define OTGSC_MSE BIT(29) /* 1 ms timer interrupt enable */
219 #define OTGSC_BSEIE BIT(28) /* B session end interrupt enable */
220 #define OTGSC_BSVIE BIT(27) /* B session valid interrupt enable */
221 #define OTGSC_ASVIE BIT(26) /* A session valid interrupt enable */
222 #define OTGSC_AVVIE BIT(25) /* A VBUS valid interrupt enable */
223 #define OTGSC_IDIE BIT(24) /* USB ID interrupt enable */
224 #define OTGSC_DPIS BIT(22) /* data pulse interrupt status */
225 #define OTGSC_MSS BIT(21) /* 1 ms timer interrupt status */
226 #define OTGSC_BSEIS BIT(20) /* B session end interrupt status */
227 #define OTGSC_BSVIS BIT(19) /* B session valid interrupt status */
228 #define OTGSC_ASVIS BIT(18) /* A session valid interrupt status */
229 #define OTGSC_AVVIS BIT(17) /* A VBUS valid interrupt status */
230 #define OTGSC_IDIS BIT(16) /* USB ID interrupt status */
231 #define OTGSC_DPS BIT(14) /* data bus pulsing status */
232 #define OTGSC_MST BIT(13) /* 1 ms timer toggle */
233 #define OTGSC_BSE BIT(12) /* B session end */
234 #define OTGSC_BSV BIT(11) /* B session valid */
235 #define OTGSC_ASV BIT(10) /* A session valid */
236 #define OTGSC_AVV BIT(9) /* A VBUS valid */
237 #define OTGSC_USBID BIT(8) /* USB ID */
238 #define OTGSC_HABA BIT(7) /* hw assist B-disconnect to A-connect */
239 #define OTGSC_HADP BIT(6) /* hw assist data pulse */
240 #define OTGSC_IDPU BIT(5) /* ID pullup */
241 #define OTGSC_DP BIT(4) /* data pulsing */
242 #define OTGSC_OT BIT(3) /* OTG termination */
243 #define OTGSC_HAAR BIT(2) /* hw assist auto reset */
244 #define OTGSC_VC BIT(1) /* VBUS charge */
245 #define OTGSC_VD BIT(0) /* VBUS discharge */
247 #define MODE_VBPS BIT(5) /* R/W VBUS power select */
248 #define MODE_SDIS BIT(4) /* R/W stream disable mode */
249 #define MODE_SLOM BIT(3) /* R/W setup lockout mode */
250 #define MODE_ENSE BIT(2) /* endian select */
293 #define EPCTRL_TXE BIT(23) /* TX endpoint enable */
294 #define EPCTRL_TXR BIT(22) /* TX data toggle reset */
295 #define EPCTRL_TXI BIT(21) /* TX data toggle inhibit */
298 #define EPCTRL_TXD BIT(17) /* TX endpoint data source */
299 #define EPCTRL_TXS BIT(16) /* TX endpoint STALL */
300 #define EPCTRL_RXE BIT(7) /* RX endpoint enable */
301 #define EPCTRL_RXR BIT(6) /* RX data toggle reset */
302 #define EPCTRL_RXI BIT(5) /* RX data toggle inhibit */
305 #define EPCTRL_RXD BIT(1) /* RX endpoint data sink */
306 #define EPCTRL_RXS BIT(0) /* RX endpoint STALL */