370 	viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);  in load_lcd_scaling()
401 			viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6);  in load_lcd_scaling()
413 		viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT7);  in load_lcd_scaling()
445 			viafb_write_reg_mask(CRA2, VIACR, 0x08, BIT3);  in load_lcd_scaling()
457 		viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT3);  in load_lcd_scaling()
547 			viafb_write_reg_mask(CR99, VIACR, 0x08,  in lcd_patch_skew()
602 			viafb_write_reg_mask(CR79, VIACR, 0x00,  in viafb_lcd_set_mode()
625 		viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0);  in viafb_lcd_set_mode()
647 		viafb_write_reg_mask(CRD4, VIACR, 0, BIT1);  in integrated_lvds_disable()
650 		viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7);  in integrated_lvds_disable()
656 		viafb_write_reg_mask(CR6A, VIACR, 0, BIT3);  in integrated_lvds_disable()
659 		viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7);  in integrated_lvds_disable()
666 			viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7);  in integrated_lvds_disable()
672 			viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6);  in integrated_lvds_disable()
678 			viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7);  in integrated_lvds_disable()
691 		viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1);  in integrated_lvds_enable()
693 		viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1);  in integrated_lvds_enable()
700 		viafb_write_reg_mask(CR91, VIACR, 0, BIT0);  in integrated_lvds_enable()
702 		viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7);  in integrated_lvds_enable()
704 		viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);  in integrated_lvds_enable()
709 		viafb_write_reg_mask(CRD3, VIACR, 0, BIT0);  in integrated_lvds_enable()
711 		viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7);  in integrated_lvds_enable()
713 		viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1);  in integrated_lvds_enable()
721 			viafb_write_reg_mask(CRD2, VIACR, 0, BIT7);  in integrated_lvds_enable()
727 			viafb_write_reg_mask(CRD2, VIACR, 0, BIT6);  in integrated_lvds_enable()
733 			viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7);  in integrated_lvds_enable()
745 		viafb_write_reg_mask(SR1E, VIASR, 0x00, 0x30);  in viafb_lcd_disable()
766 		viafb_write_reg_mask(SR3D, VIASR, 0x00, 0x20);  in viafb_lcd_disable()
768 		viafb_write_reg_mask(CR91, VIACR, 0x80, 0x80);  in viafb_lcd_disable()
772 	viafb_write_reg_mask(CR79, VIACR, 0x00, 0x01);  in viafb_lcd_disable()
774 	viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);  in viafb_lcd_disable()
784 			viafb_write_reg_mask(CR97, VIACR, 0x84,  in set_lcd_output_path()
798 	viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);  in viafb_lcd_enable()
799 	viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);  in viafb_lcd_enable()
809 		viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30);  in viafb_lcd_enable()
831 		viafb_write_reg_mask(SR3D, VIASR, 0x20, 0x20);  in viafb_lcd_enable()
833 		viafb_write_reg_mask(CR91, VIACR, 0x00, 0x80);  in viafb_lcd_enable()
835 		viafb_write_reg_mask(CR6A, VIACR, 0x48, 0x48);  in viafb_lcd_enable()
844 	viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);  in lcd_powersequence_off()
849 		viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);  in lcd_powersequence_off()
854 	viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x08);  in lcd_powersequence_off()
862 	viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);  in lcd_powersequence_on()
865 	viafb_write_reg_mask(CR6A, VIACR, 0x08, 0x08);  in lcd_powersequence_on()
870 		viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);  in lcd_powersequence_on()
886 	viafb_write_reg_mask(CR88, VIACR, (bdithering | bdual), BIT4 + BIT0);  in fill_lcd_format()