693 	viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);  in viafb_lock_crt()
698 	viafb_write_reg_mask(CR11, VIACR, 0, BIT7);  in viafb_unlock_crt()
699 	viafb_write_reg_mask(CR47, VIACR, 0, BIT0);  in viafb_unlock_crt()
891 	viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);  in viafb_set_primary_color_register()
897 	viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);  in viafb_set_secondary_color_register()
1166 	viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);  in load_fix_bit_crtc_reg()
1170 	viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);  in load_fix_bit_crtc_reg()
1172 	viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);  in load_fix_bit_crtc_reg()
1174 	viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);  in load_fix_bit_crtc_reg()
1176 	viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);  in load_fix_bit_crtc_reg()
1188 		viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);  in load_fix_bit_crtc_reg()
1191 		viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);  in load_fix_bit_crtc_reg()
1224 			viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);  in viafb_load_reg()
1226 			viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);  in viafb_load_reg()
1691 	viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);  in viafb_set_vclock()
1748 	viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);  in viafb_set_vclock()
1752 		viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);  in viafb_set_vclock()
1753 		viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);  in viafb_set_vclock()
1757 		viafb_write_reg_mask(SR40, VIASR, 0x04, BIT2);  in viafb_set_vclock()
1758 		viafb_write_reg_mask(SR40, VIASR, 0x00, BIT2);  in viafb_set_vclock()
2037 		viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);  in viafb_fill_crtc_timing()
2038 		viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);  in viafb_fill_crtc_timing()
2052 	viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);  in viafb_fill_crtc_timing()
2258 		viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);  in viafb_init_dac()
2260 		viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);  in viafb_init_dac()
2267 		viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);  in viafb_init_dac()
2271 		viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);  in viafb_init_dac()
2272 		viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);  in viafb_init_dac()
2279 		viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);  in viafb_init_dac()
2287 	viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);  in device_screen_off()
2293 	viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);  in device_screen_on()
2304 		viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);  in set_display_channel()
2308 		viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);  in set_display_channel()
2311 		viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);  in set_display_channel()
2316 			viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);  in set_display_channel()
2319 			viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);  in set_display_channel()
2401 	viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);  in viafb_setmode()
2431 			viafb_write_reg_mask(index, port, value, mask);  in viafb_setmode()
2624 	viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);  in enable_second_display_channel()
2625 	viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);  in enable_second_display_channel()
2626 	viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);  in enable_second_display_channel()
2632 	viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);  in disable_second_display_channel()
2633 	viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);  in disable_second_display_channel()
2634 	viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);  in disable_second_display_channel()
2644 			viafb_write_reg_mask(CR96, VIACR,  in viafb_set_dpa_gfx()
2648 			viafb_write_reg_mask(SR1E, VIASR,  in viafb_set_dpa_gfx()
2650 			viafb_write_reg_mask(SR2A, VIASR,  in viafb_set_dpa_gfx()
2653 			viafb_write_reg_mask(SR1B, VIASR,  in viafb_set_dpa_gfx()
2655 			viafb_write_reg_mask(SR2A, VIASR,  in viafb_set_dpa_gfx()
2663 			viafb_write_reg_mask(CR9B, VIACR,  in viafb_set_dpa_gfx()
2667 			viafb_write_reg_mask(SR65, VIASR,  in viafb_set_dpa_gfx()
2674 			viafb_write_reg_mask(CR97, VIACR,  in viafb_set_dpa_gfx()
2681 			viafb_write_reg_mask(CR99, VIACR,  in viafb_set_dpa_gfx()
2688 			viafb_write_reg_mask(CR97, VIACR,  in viafb_set_dpa_gfx()
2690 			viafb_write_reg_mask(CR99, VIACR,  in viafb_set_dpa_gfx()