Lines Matching refs:crt_reg
2001 struct display_timing crt_reg; in viafb_fill_crtc_timing() local
2017 crt_reg = crt_table[index].crtc; in viafb_fill_crtc_timing()
2026 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8; in viafb_fill_crtc_timing()
2029 crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16; in viafb_fill_crtc_timing()
2032 h_addr = crt_reg.hor_addr; in viafb_fill_crtc_timing()
2033 v_addr = crt_reg.ver_addr; in viafb_fill_crtc_timing()
2043 viafb_load_crtc_timing(crt_reg, IGA1); in viafb_fill_crtc_timing()
2046 viafb_load_crtc_timing(crt_reg, IGA2); in viafb_fill_crtc_timing()
2060 clock = crt_reg.hor_total * crt_reg.ver_total in viafb_fill_crtc_timing()
2702 struct display_timing crt_reg; in viafb_fill_var_timing_info() local
2711 crt_reg = crt_timing[index].crtc; in viafb_fill_var_timing_info()
2714 crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end); in viafb_fill_var_timing_info()
2715 var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr; in viafb_fill_var_timing_info()
2716 var->hsync_len = crt_reg.hor_sync_end; in viafb_fill_var_timing_info()
2718 crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end); in viafb_fill_var_timing_info()
2719 var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr; in viafb_fill_var_timing_info()
2720 var->vsync_len = crt_reg.ver_sync_end; in viafb_fill_var_timing_info()