74 		viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);  in viafb_tmds_trasmitter_identify()
81 		viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);  in viafb_tmds_trasmitter_identify()
84 		viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7);  in viafb_tmds_trasmitter_identify()
90 		viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 +  in viafb_tmds_trasmitter_identify()
95 		viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5);  in viafb_tmds_trasmitter_identify()
484 	viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);  in dvi_patch_skew_dvp0()
485 	viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);  in dvi_patch_skew_dvp0()
493 				viafb_write_reg_mask(CR96, VIACR, 0x03,  in dvi_patch_skew_dvp0()
496 				viafb_write_reg_mask(CR96, VIACR, 0x07,  in dvi_patch_skew_dvp0()
503 			viafb_write_reg_mask(CR96, VIACR, 0x07,  in dvi_patch_skew_dvp0()
505 			viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);  in dvi_patch_skew_dvp0()
506 			viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);  in dvi_patch_skew_dvp0()
522 			viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);  in dvi_patch_skew_dvp_low()
528 			viafb_write_reg_mask(CR99, VIACR, 0x08,  in dvi_patch_skew_dvp_low()
535 			viafb_write_reg_mask(CR99, VIACR, 0x0F,  in dvi_patch_skew_dvp_low()
554 		viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);  in viafb_dvi_enable()
555 		viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5);  in viafb_dvi_enable()
567 			viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5);  in viafb_dvi_enable()
579 			viafb_write_reg_mask(CR91, VIACR, 0x1f, 0x1f);  in viafb_dvi_enable()
580 			viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0);  in viafb_dvi_enable()
612 		viafb_write_reg_mask(CR91, VIACR, 0, BIT7);  in viafb_dvi_enable()
615 		viafb_write_reg_mask(CRD2, VIACR, 0, BIT3);  in viafb_dvi_enable()
621 		viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);  in viafb_dvi_enable()