137 #define MOD_REG_FLD(reg, mask, val) \  macro
265 	MOD_REG_FLD(DISPC_CONFIG, 0x03 << 1, mode << 1);  in set_load_mode()
272 	MOD_REG_FLD(DISPC_SIZE_LCD, FLD_MASK(16, 11) | FLD_MASK(0, 11),  in omap_dispc_set_lcd_size()
282 	MOD_REG_FLD(DISPC_SIZE_DIG, FLD_MASK(16, 11) | FLD_MASK(0, 11),  in omap_dispc_set_digit_size()
310 	MOD_REG_FLD(ftrs_reg[plane], FLD_MASK(16, 12) | FLD_MASK(0, 12),  in setup_plane_fifo()
317 	MOD_REG_FLD(DISPC_CONTROL, 1, enable ? 1 : 0);  in omap_dispc_enable_lcd_out()
325 	MOD_REG_FLD(DISPC_CONTROL, 1 << 1, enable ? 1 << 1 : 0);  in omap_dispc_enable_digit_out()
434 	MOD_REG_FLD(ps_reg[plane],  in _setup_plane()
437 	MOD_REG_FLD(sz_reg[plane], FLD_MASK(16, 11) | FLD_MASK(0, 11),  in _setup_plane()
443 			MOD_REG_FLD(vs_reg[plane],  in _setup_plane()
446 			MOD_REG_FLD(vs_reg[plane],  in _setup_plane()
570 	MOD_REG_FLD(fir_reg[plane],  in omap_dispc_set_scale()
580 	MOD_REG_FLD(vs_reg[plane],  in omap_dispc_set_scale()
603 	MOD_REG_FLD(at_reg[plane], 1, enable ? 1 : 0);  in omap_dispc_enable_plane()
642 	MOD_REG_FLD(DISPC_CONFIG, FLD_MASK(shift, 2), val << shift);  in omap_dispc_set_color_key()
734 	MOD_REG_FLD(cf1_reg,		mask,	CVAL(ct->rcr, ct->ry));  in setup_color_conv_coef()
735 	MOD_REG_FLD(cf1_reg + 4,	mask,	CVAL(ct->gy,  ct->rcb));  in setup_color_conv_coef()
736 	MOD_REG_FLD(cf1_reg + 8,	mask,	CVAL(ct->gcb, ct->gcr));  in setup_color_conv_coef()
737 	MOD_REG_FLD(cf1_reg + 12,	mask,	CVAL(ct->bcr, ct->by));  in setup_color_conv_coef()
738 	MOD_REG_FLD(cf1_reg + 16,	mask,	CVAL(0,	      ct->bcb));  in setup_color_conv_coef()
740 	MOD_REG_FLD(cf2_reg,		mask,	CVAL(ct->rcr, ct->ry));  in setup_color_conv_coef()
741 	MOD_REG_FLD(cf2_reg + 4,	mask,	CVAL(ct->gy,  ct->rcb));  in setup_color_conv_coef()
742 	MOD_REG_FLD(cf2_reg + 8,	mask,	CVAL(ct->gcb, ct->gcr));  in setup_color_conv_coef()
743 	MOD_REG_FLD(cf2_reg + 12,	mask,	CVAL(ct->bcr, ct->by));  in setup_color_conv_coef()
744 	MOD_REG_FLD(cf2_reg + 16,	mask,	CVAL(0,	      ct->bcb));  in setup_color_conv_coef()
747 	MOD_REG_FLD(at1_reg, (1 << 11), ct->full_range);  in setup_color_conv_coef()
748 	MOD_REG_FLD(at2_reg, (1 << 11), ct->full_range);  in setup_color_conv_coef()
782 	MOD_REG_FLD(DISPC_CONTROL, mask, enable ? mask : 0);  in set_lcd_tft_mode()
838 	MOD_REG_FLD(DISPC_IRQENABLE, 0x7fff, irq_mask);  in recalc_irq_mask()
1416 		MOD_REG_FLD(DISPC_SYSCONFIG, 1 << 1, 1 << 1);  in omap_dispc_init()
1475 		MOD_REG_FLD(DISPC_DIVISOR, FLD_MASK(16, 8), 1 << 16);  in omap_dispc_init()
1476 		MOD_REG_FLD(DISPC_DIVISOR, FLD_MASK(0, 8), 2 << 0);  in omap_dispc_init()