Lines Matching refs:DISPC_VID2_BASE
84 #define DISPC_VID2_BASE 0x014C macro
292 DISPC_VID2_BASE + DISPC_VID_FIFO_THRESHOLD }; in setup_plane_fifo()
295 DISPC_VID2_BASE + DISPC_VID_FIFO_SIZE_STATUS }; in setup_plane_fifo()
337 DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES }; in _setup_plane()
339 DISPC_VID2_BASE + DISPC_VID_BA0 }; in _setup_plane()
342 DISPC_VID2_BASE + DISPC_VID_POSITION }; in _setup_plane()
345 DISPC_VID2_BASE + DISPC_VID_PICTURE_SIZE }; in _setup_plane()
348 DISPC_VID2_BASE + DISPC_VID_ROW_INC }; in _setup_plane()
350 DISPC_VID2_BASE + DISPC_VID_SIZE }; in _setup_plane()
482 base = DISPC_VID2_BASE + DISPC_VID_FIR_COEF_H0; in write_firh_reg()
493 base = DISPC_VID2_BASE + DISPC_VID_FIR_COEF_HV0; in write_firhv_reg()
522 DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES }; in omap_dispc_set_scale()
524 DISPC_VID2_BASE + DISPC_VID_SIZE }; in omap_dispc_set_scale()
526 DISPC_VID2_BASE + DISPC_VID_FIR }; in omap_dispc_set_scale()
598 DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES }; in omap_dispc_enable_plane()
720 int cf2_reg = DISPC_VID2_BASE + DISPC_VID_CONV_COEF0; in setup_color_conv_coef()
722 int at2_reg = DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES; in setup_color_conv_coef()