Lines Matching refs:TVP3026_XPLLADDR
203 #define TVP3026_XPLLADDR 0x2C macro
454 outTi3026(minfo, TVP3026_XPLLADDR, 0xFC); in ti3026_setMCLK()
456 outTi3026(minfo, TVP3026_XPLLADDR, 0xFD); in ti3026_setMCLK()
458 outTi3026(minfo, TVP3026_XPLLADDR, 0xFE); in ti3026_setMCLK()
462 outTi3026(minfo, TVP3026_XPLLADDR, 0xFE); in ti3026_setMCLK()
466 outTi3026(minfo, TVP3026_XPLLADDR, 0xFC); in ti3026_setMCLK()
486 outTi3026(minfo, TVP3026_XPLLADDR, 0xFB); in ti3026_setMCLK()
490 outTi3026(minfo, TVP3026_XPLLADDR, 0xF3); in ti3026_setMCLK()
522 outTi3026(minfo, TVP3026_XPLLADDR, 0xFE); in ti3026_setMCLK()
526 outTi3026(minfo, TVP3026_XPLLADDR, 0xFC); in ti3026_setMCLK()
591 outTi3026(minfo, TVP3026_XPLLADDR, 0x00); in Ti3026_restore()
594 outTi3026(minfo, TVP3026_XPLLADDR, 0x15); in Ti3026_restore()
597 outTi3026(minfo, TVP3026_XPLLADDR, 0x2A); in Ti3026_restore()
609 outTi3026(minfo, TVP3026_XPLLADDR, 0x2A); in Ti3026_restore()
613 outTi3026(minfo, TVP3026_XPLLADDR, 0x00); in Ti3026_restore()
619 outTi3026(minfo, TVP3026_XPLLADDR, 0x3F); in Ti3026_restore()
635 outTi3026(minfo, TVP3026_XPLLADDR, 0x00); in Ti3026_restore()
643 outTi3026(minfo, TVP3026_XPLLADDR, 0x3F); in Ti3026_restore()
723 outTi3026(minfo, TVP3026_XPLLADDR, 0x2A); in Ti3026_preinit()