Lines Matching refs:STG_WRITE_REG
102 STG_WRITE_REG(SDRAMArbiterConf, adwSDRAMArgCfg0[dwMemTypeIdx]); in InitSDRAMRegisters()
104 STG_WRITE_REG(SDRAMConf0, 0x49A1); in InitSDRAMRegisters()
105 STG_WRITE_REG(SDRAMConf1, adwSDRAMCfg1[dwMemTypeIdx]); in InitSDRAMRegisters()
107 STG_WRITE_REG(SDRAMConf0, 0x4DF1); in InitSDRAMRegisters()
108 STG_WRITE_REG(SDRAMConf1, adwSDRAMCfg2[dwMemTypeIdx]); in InitSDRAMRegisters()
111 STG_WRITE_REG(SDRAMConf2, 0x31); in InitSDRAMRegisters()
112 STG_WRITE_REG(SDRAMRefresh, adwSDRAMRsh[dwChipSpeedIdx]); in InitSDRAMRegisters()
251 STG_WRITE_REG(IntMask, 0xFFFF); in SetCoreClockPLL()
256 STG_WRITE_REG(Thread0Enable, tmp); in SetCoreClockPLL()
261 STG_WRITE_REG(Thread1Enable, tmp); in SetCoreClockPLL()
263 STG_WRITE_REG(SoftwareReset, in SetCoreClockPLL()
265 STG_WRITE_REG(SoftwareReset, in SetCoreClockPLL()
270 STG_WRITE_REG(TAConfiguration, 0); in SetCoreClockPLL()
271 STG_WRITE_REG(SoftwareReset, in SetCoreClockPLL()
273 STG_WRITE_REG(SoftwareReset, in SetCoreClockPLL()
313 STG_WRITE_REG(SoftwareReset, PMX2_SOFTRESET_ALL); in SetCoreClockPLL()
318 STG_WRITE_REG(Thread0Enable, tmp); in SetCoreClockPLL()
322 STG_WRITE_REG(Thread1Enable, tmp); in SetCoreClockPLL()