430 	wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
432 	wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
437 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
1429 	wr_reg16(info, TCR, value);  in set_break()
2170 	wr_reg16(info, SSR, status); /* clear pending */  in isr_serial()
2310 		wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */  in isr_txeom()
2311 		wr_reg16(info, TCR, val); /* clear reset bit */  in isr_txeom()
2754 			wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);  in rx_enable()
2807 			wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));  in wait_mgsl_event()
2870 			wr_reg16(info, SCR,  in wait_mgsl_event()
2906 	wr_reg16(info, TCR, val);  in set_interface()
3876 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)  in wr_reg16()  function
3928 	wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));  in enable_loopback()
3967 		wr_reg16(info, BDR, (unsigned short)div);  in set_rate()
3977 	wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */  in rx_stop()
3978 	wr_reg16(info, RCR, val);                  /* clear reset bit */  in rx_stop()
3983 	wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);  in rx_stop()
3998 	wr_reg16(info, SSR, IRQ_RXOVER);  in rx_start()
4002 	wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */  in rx_start()
4003 	wr_reg16(info, RCR, val);                  /* clear reset bit */  in rx_start()
4010 		wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));  in rx_start()
4018 		wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));  in rx_start()
4034 	wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));  in rx_start()
4043 		wr_reg16(info, TCR,  in tx_start()
4064 			wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));  in tx_start()
4069 			wr_reg16(info, SSR, IRQ_TXIDLE);  in tx_start()
4088 	wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */  in tx_stop()
4093 	wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));  in tx_stop()
4174 	wr_reg16(info, TCR, val);  in async_mode()
4211 	wr_reg16(info, RCR, val);  in async_mode()
4257 	wr_reg16(info, SCR, val);  in async_mode()
4336 	wr_reg16(info, TCR, val);  in sync_mode()
4399 	wr_reg16(info, RCR, val);  in sync_mode()
4450 		wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));  in sync_mode()
4481 	wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);  in sync_mode()
4508 	wr_reg16(info, TCR, tcr);  in tx_set_idle()
4969 		wr_reg16(info, TIR, patterns[i]);  in register_test()
4970 		wr_reg16(info, BDR, patterns[(i+1)%count]);  in register_test()
4997 	wr_reg16(info, TCR,  in irq_test()
5001 	wr_reg16(info, TDR, 0);  in irq_test()