335 	unsigned long imr_reg;  member
703 	msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);  in msm_hs_set_termios()
820 	msm_uport->imr_reg &= ~UARTDM_ISR_TX_READY_BMSK;  in msm_hs_submit_tx_locked()
821 	msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);  in msm_hs_submit_tx_locked()
833 	msm_uport->imr_reg |= UARTDM_ISR_RXLEV_BMSK;  in msm_hs_start_rx_locked()
834 	msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);  in msm_hs_start_rx_locked()
885 	msm_uport->imr_reg |= UARTDM_ISR_TX_READY_BMSK;  in msm_hs_dmov_tx_callback()
886 	msm_hs_write(&msm_uport->uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);  in msm_hs_dmov_tx_callback()
1053 	msm_uport->imr_reg |= UARTDM_ISR_DELTA_CTS_BMSK;  in msm_hs_enable_ms_locked()
1054 	msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);  in msm_hs_enable_ms_locked()
1122 	    (msm_uport->imr_reg & UARTDM_ISR_TXLEV_BMSK) ||  in msm_hs_check_clock_off_locked()
1123 	    !(msm_uport->imr_reg & UARTDM_ISR_RXLEV_BMSK))  {  in msm_hs_check_clock_off_locked()
1198 		msm_uport->imr_reg &= ~UARTDM_ISR_RXLEV_BMSK;  in msm_hs_isr()
1199 		msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);  in msm_hs_isr()
1220 			msm_uport->imr_reg |= UARTDM_ISR_TXLEV_BMSK;  in msm_hs_isr()
1222 				     msm_uport->imr_reg);  in msm_hs_isr()
1239 		msm_uport->imr_reg &= ~UARTDM_ISR_TXLEV_BMSK;  in msm_hs_isr()
1240 		msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);  in msm_hs_isr()
1265 		msm_uport->imr_reg |= UARTDM_ISR_TXLEV_BMSK;  in msm_hs_request_clock_off_locked()
1266 		msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);  in msm_hs_request_clock_off_locked()
1479 	msm_uport->imr_reg |= UARTDM_ISR_RXSTALE_BMSK;  in msm_hs_startup()
1481 	msm_uport->imr_reg |= UARTDM_ISR_CURRENT_CTS_BMSK;  in msm_hs_startup()
1691 	msm_uport->imr_reg = 0x0;  in msm_hs_probe()
1772 	msm_uport->imr_reg = 0;  in msm_hs_shutdown()
1773 	msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);  in msm_hs_shutdown()