59 #define UCR1  0x80 /* Control Register 1 */  macro
277 			temp = readl(sport->port.membase + UCR1);  in imx_stop_tx()
279 			writel(temp, sport->port.membase + UCR1);  in imx_stop_tx()
289 			temp = readl(sport->port.membase + UCR1);  in imx_stop_tx()
291 			writel(temp, sport->port.membase + UCR1);  in imx_stop_tx()
300 	temp = readl(sport->port.membase + UCR1);  in imx_stop_tx()
301 	writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);  in imx_stop_tx()
360 		temp = readl(sport->port.membase + UCR1);  in imx_start_tx()
362 		writel(temp, sport->port.membase + UCR1);  in imx_start_tx()
365 	temp = readl(sport->port.membase + UCR1);  in imx_start_tx()
366 	writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);  in imx_start_tx()
369 		temp = readl(sport->port.membase + UCR1);  in imx_start_tx()
371 		writel(temp, sport->port.membase + UCR1);  in imx_start_tx()
501 			readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)  in imx_int()
560 	temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;  in imx_break_ctl()
565 	writel(temp, sport->port.membase + UCR1);  in imx_break_ctl()
671 	temp = readl(sport->port.membase + UCR1);  in imx_startup()
679 	writel(temp, sport->port.membase + UCR1);  in imx_startup()
781 	temp = readl(sport->port.membase + UCR1);  in imx_shutdown()
786 	writel(temp, sport->port.membase + UCR1);  in imx_shutdown()
882 	old_ucr1 = readl(sport->port.membase + UCR1);  in imx_set_termios()
884 			sport->port.membase + UCR1);  in imx_set_termios()
932 	writel(old_ucr1, sport->port.membase + UCR1);  in imx_set_termios()
1065 	ucr1 = old_ucr1 = readl(sport->port.membase + UCR1);  in imx_console_write()
1073 	writel(ucr1, sport->port.membase + UCR1);  in imx_console_write()
1085 	writel(old_ucr1, sport->port.membase + UCR1);  in imx_console_write()
1098 	if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {  in imx_console_get_options()