Lines Matching defs:qla81xx_fw_dump

269 struct qla81xx_fw_dump {  struct
270 	uint32_t host_status;
271 	uint32_t host_risc_reg[32];
272 	uint32_t pcie_regs[4];
273 	uint32_t host_reg[32];
274 	uint32_t shadow_reg[11];
275 	uint32_t risc_io_reg;
276 	uint16_t mailbox_reg[32];
277 	uint32_t xseq_gp_reg[128];
278 	uint32_t xseq_0_reg[48];
279 	uint32_t xseq_1_reg[16];
280 	uint32_t rseq_gp_reg[128];
281 	uint32_t rseq_0_reg[32];
282 	uint32_t rseq_1_reg[16];
283 	uint32_t rseq_2_reg[16];
284 	uint32_t aseq_gp_reg[128];
285 	uint32_t aseq_0_reg[32];
286 	uint32_t aseq_1_reg[16];
287 	uint32_t aseq_2_reg[16];
288 	uint32_t cmd_dma_reg[16];
289 	uint32_t req0_dma_reg[15];
290 	uint32_t resp0_dma_reg[15];
291 	uint32_t req1_dma_reg[15];
292 	uint32_t xmt0_dma_reg[32];
293 	uint32_t xmt1_dma_reg[32];
294 	uint32_t xmt2_dma_reg[32];
295 	uint32_t xmt3_dma_reg[32];
296 	uint32_t xmt4_dma_reg[32];
297 	uint32_t xmt_data_dma_reg[16];
298 	uint32_t rcvt0_data_dma_reg[32];
299 	uint32_t rcvt1_data_dma_reg[32];
300 	uint32_t risc_gp_reg[128];
301 	uint32_t lmc_reg[128];
302 	uint32_t fpm_hdw_reg[224];
303 	uint32_t fb_hdw_reg[208];
304 	uint32_t code_ram[0x2000];
305 	uint32_t ext_mem[1];