Lines Matching defs:rtl818x_csr

18 struct rtl818x_csr {  struct
19 	u8	MAC[6];
20 	u8	reserved_0[2];
21 	__le32	MAR[2];
22 	u8	RX_FIFO_COUNT;
23 	u8	reserved_1;
24 	u8	TX_FIFO_COUNT;
25 	u8	BQREQ;
26 	u8	reserved_2[4];
27 	__le32	TSFT[2];
28 	__le32	TLPDA;
29 	__le32	TNPDA;
30 	__le32	THPDA;
31 	__le16	BRSR;
32 	u8	BSSID[6];
33 	u8	RESP_RATE;
34 	u8	EIFS;
35 	u8	reserved_3[1];
36 	u8	CMD;
40 	u8	reserved_4[4];
41 	__le16	INT_MASK;
42 	__le16	INT_STATUS;
59 	__le32	TX_CONF;
76 	__le32	RX_CONF;
92 	__le32	INT_TIMEOUT;
93 	__le32	TBDA;
94 	u8	EEPROM_CMD;
103 	u8	CONFIG0;
104 	u8	CONFIG1;
105 	u8	CONFIG2;
107 	__le32	ANAPARAM;
108 	u8	MSR;
114 	u8	CONFIG3;
117 	u8	CONFIG4;
120 	u8	TESTR;
121 	u8	reserved_9[2];
122 	u8	PGSELECT;
123 	u8	SECURITY;
124 	__le32	ANAPARAM2;
125 	u8	reserved_10[12];
126 	__le16	BEACON_INTERVAL;
127 	__le16	ATIM_WND;
128 	__le16	BEACON_INTERVAL_TIME;
129 	__le16	ATIMTR_INTERVAL;
130 	u8	PHY_DELAY;
131 	u8	CARRIER_SENSE_COUNTER;
132 	u8	reserved_11[2];
133 	u8	PHY[4];
134 	__le16	RFPinsOutput;
135 	__le16	RFPinsEnable;
136 	__le16	RFPinsSelect;
137 	__le16	RFPinsInput;
138 	__le32	RF_PARA;
139 	__le32	RF_TIMING;
140 	u8	GP_ENABLE;
141 	u8	GPIO0;
142 	u8	GPIO1;
143 	u8	reserved_12;
144 	__le32	HSSI_PARA;
145 	u8	reserved_13[4];
146 	u8	TX_AGC_CTL;
150 	u8	TX_GAIN_CCK;
151 	u8	TX_GAIN_OFDM;
152 	u8	TX_ANTENNA;
153 	u8	reserved_14[16];
154 	u8	WPA_CONF;
155 	u8	reserved_15[3];
156 	u8	SIFS;
157 	u8	DIFS;
158 	u8	SLOT;
159 	u8	reserved_16[5];
160 	u8	CW_CONF;
163 	u8	CW_VAL;
164 	u8	RATE_FALLBACK;
166 	u8	ACM_CONTROL;
167 	u8	reserved_17[24];
168 	u8	CONFIG5;
169 	u8	TX_DMA_POLLING;
170 	u8	reserved_18[2];
171 	__le16	CWR;
172 	u8	RETRY_CTR;
173 	u8	reserved_19[3];
174 	__le16	INT_MIG;
179 	__le32	RDSAR;
180 	__le16	TID_AC_MAP;
181 	u8	reserved_20[4];
182 	u8	ANAPARAM3;
183 	u8	reserved_21[5];
184 	__le16	FEMR;
185 	u8	reserved_22[4];
186 	__le16	TALLY_CNT;
187 	u8	TALLY_SEL;