Lines Matching refs:movew

159 	movew (\src)+, (\dest)+
222 	movew #(TIMER_IRQ_LEVEL << 8) + TIMER_IRQ, PICR	// interrupt from PIT
223 	movew #PITR_CONST, PITR
242 	movew #0xFFFF, PAPAR		// all pins are clocks/data
256 	movew #0x2700, %sr		// disable IRQs again
354 	movew %d1, SCC_TBASE(%a1)	// D1 = offset of first TxBD
356 	movew %d1, SCC_RBASE(%a1)	// D1 = offset of first RxBD
366 	movew #HDLC_MAX_MRU + 2, SCC_MFLR(%a1) // 2 bytes for CRC
367 	movew #2, parity_bytes(%d0)
373 	movew #0x0800, SCC_PSMR(%a2)	// CRC32-CCITT
376 	movew #HDLC_MAX_MRU + 4, SCC_MFLR(%a1) // 4 bytes for CRC
377 	movew #4, parity_bytes(%d0)
386 	movew #HDLC_MAX_MRU + 2, SCC_MFLR(%a1) // 2 bytes for CRC
387 	movew #2, parity_bytes(%d0)
393 	movew #0x0800, SCC_PSMR(%a2)	// CRC32-CCITT preset 0
396 	movew #HDLC_MAX_MRU + 4, SCC_MFLR(%a1) // 4 bytes for CRC
397 	movew #4, parity_bytes(%d0)
404 	movew #HDLC_MAX_MRU, SCC_MFLR(%a1) // 0 bytes for CRC
417 	movew #BUFFER_LENGTH, SCC_MRBLR(%a1)
421 	movew %d1, CR			// Init SCC RX and TX params
425 	movew #0x001F, SCC_SCCM(%a2)	// TXE RXF BSY TXB RXB interrupts
467 	movew %d2, 2(%d1)		// length into BD
491 	movew (%d1), %d2		// D2 = RX BD flags
506 	movew 2(%d1), %d3
571 	movew (%d1), %d3		// D3 = TX BD flags
608 	movew %sr, -(%sp)
614 	movew #0x2700, %sr		// disable interrupts again
619 	movew %sr, -(%sp)
625 	movew #0x2700, %sr		// disable interrupts again
629 	movew (%sp)+, %sr
696 	movew (%a0), %d1		// D1 = CSR input bits
700 	movew #0x0E08, %d1
706 	movew #0x0408, %d1
712 	movew #0x0208, %d1
718 	movew #0x0D08, %d1
722 	movew #0x0008, %d1		// D1 = disable everything
723 	movew #0x80E7, %d2		// D2 = input mask: ignore DSR
727 	movew csr_output(%d0), %d2
730 	movew #0x80FF, %d2		// D2 = input mask: include DSR
735 	movew %d1, old_csr_output(%d0)
736 	movew %d1, (%a0)		// Write CSR output bits
739 	movew (PCDAT), %d1
742 	movew (%a0), %d1		// D1 = CSR input bits
747 	movew (%a0), %d1		// D1 = CSR input bits