Lines Matching refs:s2BIT
23 #define GEN_INTR_TXPIC s2BIT(0)
24 #define GEN_INTR_TXDMA s2BIT(1)
25 #define GEN_INTR_TXMAC s2BIT(2)
26 #define GEN_INTR_TXXGXS s2BIT(3)
27 #define GEN_INTR_TXTRAFFIC s2BIT(8)
28 #define GEN_INTR_RXPIC s2BIT(32)
29 #define GEN_INTR_RXDMA s2BIT(33)
30 #define GEN_INTR_RXMAC s2BIT(34)
31 #define GEN_INTR_MC s2BIT(35)
32 #define GEN_INTR_RXXGXS s2BIT(36)
33 #define GEN_INTR_RXTRAFFIC s2BIT(40)
57 #define ADAPTER_STATUS_TDMA_READY s2BIT(0)
58 #define ADAPTER_STATUS_RDMA_READY s2BIT(1)
59 #define ADAPTER_STATUS_PFC_READY s2BIT(2)
60 #define ADAPTER_STATUS_TMAC_BUF_EMPTY s2BIT(3)
61 #define ADAPTER_STATUS_PIC_QUIESCENT s2BIT(5)
62 #define ADAPTER_STATUS_RMAC_REMOTE_FAULT s2BIT(6)
63 #define ADAPTER_STATUS_RMAC_LOCAL_FAULT s2BIT(7)
67 #define ADAPTER_STATUS_MC_DRAM_READY s2BIT(24)
68 #define ADAPTER_STATUS_MC_QUEUES_READY s2BIT(25)
69 #define ADAPTER_STATUS_RIC_RUNNING s2BIT(26)
70 #define ADAPTER_STATUS_M_PLL_LOCK s2BIT(30)
71 #define ADAPTER_STATUS_P_PLL_LOCK s2BIT(31)
74 #define ADAPTER_CNTL_EN s2BIT(7)
75 #define ADAPTER_EOI_TX_ON s2BIT(15)
76 #define ADAPTER_LED_ON s2BIT(23)
78 #define ADAPTER_WAIT_INT s2BIT(48)
79 #define ADAPTER_ECC_EN s2BIT(55)
82 #define SERR_SOURCE_PIC s2BIT(0)
83 #define SERR_SOURCE_TXDMA s2BIT(1)
84 #define SERR_SOURCE_RXDMA s2BIT(2)
85 #define SERR_SOURCE_MAC s2BIT(3)
86 #define SERR_SOURCE_MC s2BIT(4)
87 #define SERR_SOURCE_XGXS s2BIT(5)
105 #define PCI_MODE_UNSUPPORTED s2BIT(0)
106 #define PCI_MODE_32_BITS s2BIT(8)
107 #define PCI_MODE_UNKNOWN_MODE s2BIT(9)
114 #define PIC_INT_TX s2BIT(0)
115 #define PIC_INT_FLSH s2BIT(1)
116 #define PIC_INT_MDIO s2BIT(2)
117 #define PIC_INT_IIC s2BIT(3)
118 #define PIC_INT_GPIO s2BIT(4)
119 #define PIC_INT_RX s2BIT(32)
123 #define PCIX_INT_REG_ECC_SG_ERR s2BIT(0)
124 #define PCIX_INT_REG_ECC_DB_ERR s2BIT(1)
125 #define PCIX_INT_REG_FLASHR_R_FSM_ERR s2BIT(8)
126 #define PCIX_INT_REG_FLASHR_W_FSM_ERR s2BIT(9)
127 #define PCIX_INT_REG_INI_TX_FSM_SERR s2BIT(10)
128 #define PCIX_INT_REG_INI_TXO_FSM_ERR s2BIT(11)
129 #define PCIX_INT_REG_TRT_FSM_SERR s2BIT(13)
130 #define PCIX_INT_REG_SRT_FSM_SERR s2BIT(14)
131 #define PCIX_INT_REG_PIFR_FSM_SERR s2BIT(15)
132 #define PCIX_INT_REG_WRC_TX_SEND_FSM_SERR s2BIT(21)
133 #define PCIX_INT_REG_RRC_TX_REQ_FSM_SERR s2BIT(23)
134 #define PCIX_INT_REG_INI_RX_FSM_SERR s2BIT(48)
135 #define PCIX_INT_REG_RA_RX_FSM_SERR s2BIT(50)
148 #define PIC_FLSH_INT_REG_CYCLE_FSM_ERR s2BIT(63)
149 #define PIC_FLSH_INT_REG_ERR s2BIT(62)
154 #define MDIO_INT_REG_MDIO_BUS_ERR s2BIT(0)
155 #define MDIO_INT_REG_DTX_BUS_ERR s2BIT(8)
156 #define MDIO_INT_REG_LASI s2BIT(39)
161 #define IIC_INT_REG_BUS_FSM_ERR s2BIT(4)
162 #define IIC_INT_REG_BIT_FSM_ERR s2BIT(5)
163 #define IIC_INT_REG_CYCLE_FSM_ERR s2BIT(6)
164 #define IIC_INT_REG_REQ_FSM_ERR s2BIT(7)
165 #define IIC_INT_REG_ACK_ERR s2BIT(8)
171 #define GPIO_INT_REG_DP_ERR_INT s2BIT(0)
172 #define GPIO_INT_REG_LINK_DOWN s2BIT(1)
173 #define GPIO_INT_REG_LINK_UP s2BIT(2)
175 #define GPIO_INT_MASK_LINK_DOWN s2BIT(1)
176 #define GPIO_INT_MASK_LINK_UP s2BIT(2)
182 #define TX_TRAFFIC_INT_n(n) s2BIT(n)
186 #define RX_TRAFFIC_INT_n(n) s2BIT(n)
191 #define PIC_CNTL_RX_ALARM_MAP_1 s2BIT(0)
195 #define SWAPPER_CTRL_PIF_R_FE s2BIT(0)
196 #define SWAPPER_CTRL_PIF_R_SE s2BIT(1)
197 #define SWAPPER_CTRL_PIF_W_FE s2BIT(8)
198 #define SWAPPER_CTRL_PIF_W_SE s2BIT(9)
199 #define SWAPPER_CTRL_TXP_FE s2BIT(16)
200 #define SWAPPER_CTRL_TXP_SE s2BIT(17)
201 #define SWAPPER_CTRL_TXD_R_FE s2BIT(18)
202 #define SWAPPER_CTRL_TXD_R_SE s2BIT(19)
203 #define SWAPPER_CTRL_TXD_W_FE s2BIT(20)
204 #define SWAPPER_CTRL_TXD_W_SE s2BIT(21)
205 #define SWAPPER_CTRL_TXF_R_FE s2BIT(22)
206 #define SWAPPER_CTRL_TXF_R_SE s2BIT(23)
207 #define SWAPPER_CTRL_RXD_R_FE s2BIT(32)
208 #define SWAPPER_CTRL_RXD_R_SE s2BIT(33)
209 #define SWAPPER_CTRL_RXD_W_FE s2BIT(34)
210 #define SWAPPER_CTRL_RXD_W_SE s2BIT(35)
211 #define SWAPPER_CTRL_RXF_W_FE s2BIT(36)
212 #define SWAPPER_CTRL_RXF_W_SE s2BIT(37)
213 #define SWAPPER_CTRL_XMSI_FE s2BIT(40)
214 #define SWAPPER_CTRL_XMSI_SE s2BIT(41)
215 #define SWAPPER_CTRL_STATS_FE s2BIT(48)
216 #define SWAPPER_CTRL_STATS_SE s2BIT(49)
222 #define SCHED_INT_CTRL_TIMER_EN s2BIT(0)
223 #define SCHED_INT_CTRL_ONE_SHOT s2BIT(1)
229 #define TXREQTO_EN s2BIT(63)
233 #define STATREQTO_EN s2BIT(63)
259 #define STAT_CFG_STAT_EN s2BIT(0)
260 #define STAT_CFG_ONE_SHOT_EN s2BIT(1)
261 #define STAT_CFG_STAT_NS_EN s2BIT(8)
262 #define STAT_CFG_STAT_RO s2BIT(9)
289 #define I2C_CONTROL_READ s2BIT(24)
290 #define I2C_CONTROL_NACK s2BIT(25)
297 #define GPIO_CTRL_GPIO_0 s2BIT(8)
299 #define FAULT_BEHAVIOUR s2BIT(0)
300 #define EXT_REQ_EN s2BIT(1)
316 #define TXDMA_PFC_INT s2BIT(0)
317 #define TXDMA_TDA_INT s2BIT(1)
318 #define TXDMA_PCC_INT s2BIT(2)
319 #define TXDMA_TTI_INT s2BIT(3)
320 #define TXDMA_LSO_INT s2BIT(4)
321 #define TXDMA_TPA_INT s2BIT(5)
322 #define TXDMA_SM_INT s2BIT(6)
324 #define PFC_ECC_SG_ERR s2BIT(7)
325 #define PFC_ECC_DB_ERR s2BIT(15)
326 #define PFC_SM_ERR_ALARM s2BIT(23)
327 #define PFC_MISC_0_ERR s2BIT(31)
328 #define PFC_MISC_1_ERR s2BIT(32)
329 #define PFC_PCIX_ERR s2BIT(39)
336 #define TDA_SM0_ERR_ALARM s2BIT(22)
337 #define TDA_SM1_ERR_ALARM s2BIT(23)
338 #define TDA_PCIX_ERR s2BIT(39)
350 #define PCC_6_COF_OV_ERR s2BIT(56)
351 #define PCC_7_COF_OV_ERR s2BIT(57)
352 #define PCC_6_LSO_OV_ERR s2BIT(58)
353 #define PCC_7_LSO_OV_ERR s2BIT(59)
359 #define TTI_ECC_SG_ERR s2BIT(7)
360 #define TTI_ECC_DB_ERR s2BIT(15)
361 #define TTI_SM_ERR_ALARM s2BIT(23)
366 #define LSO6_SEND_OFLOW s2BIT(12)
367 #define LSO7_SEND_OFLOW s2BIT(13)
368 #define LSO6_ABORT s2BIT(14)
369 #define LSO7_ABORT s2BIT(15)
370 #define LSO6_SM_ERR_ALARM s2BIT(22)
371 #define LSO7_SM_ERR_ALARM s2BIT(23)
376 #define TPA_TX_FRM_DROP s2BIT(7)
377 #define TPA_SM_ERR_ALARM s2BIT(23)
383 #define SM_SM_ERR_ALARM s2BIT(15)
396 #define TX_FIFO_PARTITION_EN s2BIT(0)
436 #define TTI_CMD_MEM_WE s2BIT(7)
437 #define TTI_CMD_MEM_STROBE_NEW_CMD s2BIT(15)
438 #define TTI_CMD_MEM_STROBE_BEING_EXECUTED s2BIT(15)
444 #define TTI_DATA1_MEM_TX_TIMER_AC_EN s2BIT(38)
445 #define TTI_DATA1_MEM_TX_TIMER_CI_EN s2BIT(39)
458 #define TX_PA_CFG_IGNORE_FRM_ERR s2BIT(1)
459 #define TX_PA_CFG_IGNORE_SNAP_OUI s2BIT(2)
460 #define TX_PA_CFG_IGNORE_LLC_CTRL s2BIT(3)
461 #define TX_PA_CFG_IGNORE_L2_ERR s2BIT(6)
462 #define RX_PA_CFG_STRIP_VLAN_TAG s2BIT(15)
476 #define RXDMA_INT_RC_INT_M s2BIT(0)
477 #define RXDMA_INT_RPA_INT_M s2BIT(1)
478 #define RXDMA_INT_RDA_INT_M s2BIT(2)
479 #define RXDMA_INT_RTI_INT_M s2BIT(3)
484 #define RDA_FRM_ECC_SG_ERR s2BIT(23)
485 #define RDA_FRM_ECC_DB_N_AERR s2BIT(31)
486 #define RDA_SM1_ERR_ALARM s2BIT(38)
487 #define RDA_SM0_ERR_ALARM s2BIT(39)
488 #define RDA_MISC_ERR s2BIT(47)
489 #define RDA_PCIX_ERR s2BIT(55)
490 #define RDA_RXD_ECC_DB_SERR s2BIT(63)
497 #define RC_FTC_ECC_SG_ERR s2BIT(23)
498 #define RC_FTC_ECC_DB_ERR s2BIT(31)
500 #define RC_FTC_SM_ERR_ALARM s2BIT(47)
516 #define RPA_ECC_SG_ERR s2BIT(7)
517 #define RPA_ECC_DB_ERR s2BIT(15)
518 #define RPA_FLUSH_REQUEST s2BIT(22)
519 #define RPA_SM_ERR_ALARM s2BIT(23)
520 #define RPA_CREDIT_ERR s2BIT(31)
525 #define RTI_ECC_SG_ERR s2BIT(7)
526 #define RTI_ECC_DB_ERR s2BIT(15)
527 #define RTI_SM_ERR_ALARM s2BIT(23)
567 #define PRC_CTRL_RC_ENABLED s2BIT(7)
568 #define PRC_CTRL_RING_MODE (s2BIT(14)|s2BIT(15))
573 #define PRC_CTRL_NO_SNOOP (s2BIT(22)|s2BIT(23))
574 #define PRC_CTRL_NO_SNOOP_DESC s2BIT(22)
575 #define PRC_CTRL_NO_SNOOP_BUFF s2BIT(23)
576 #define PRC_CTRL_BIMODAL_INTERRUPT s2BIT(37)
577 #define PRC_CTRL_GROUP_READS s2BIT(38)
581 #define PRC_ALARM_ACTION_RR_R0_STOP s2BIT(3)
582 #define PRC_ALARM_ACTION_RW_R0_STOP s2BIT(7)
583 #define PRC_ALARM_ACTION_RR_R1_STOP s2BIT(11)
584 #define PRC_ALARM_ACTION_RW_R1_STOP s2BIT(15)
585 #define PRC_ALARM_ACTION_RR_R2_STOP s2BIT(19)
586 #define PRC_ALARM_ACTION_RW_R2_STOP s2BIT(23)
587 #define PRC_ALARM_ACTION_RR_R3_STOP s2BIT(27)
588 #define PRC_ALARM_ACTION_RW_R3_STOP s2BIT(31)
589 #define PRC_ALARM_ACTION_RR_R4_STOP s2BIT(35)
590 #define PRC_ALARM_ACTION_RW_R4_STOP s2BIT(39)
591 #define PRC_ALARM_ACTION_RR_R5_STOP s2BIT(43)
592 #define PRC_ALARM_ACTION_RW_R5_STOP s2BIT(47)
593 #define PRC_ALARM_ACTION_RR_R6_STOP s2BIT(51)
594 #define PRC_ALARM_ACTION_RW_R6_STOP s2BIT(55)
595 #define PRC_ALARM_ACTION_RR_R7_STOP s2BIT(59)
596 #define PRC_ALARM_ACTION_RW_R7_STOP s2BIT(63)
600 #define RTI_CMD_MEM_WE s2BIT(7)
601 #define RTI_CMD_MEM_STROBE s2BIT(15)
602 #define RTI_CMD_MEM_STROBE_NEW_CMD s2BIT(15)
603 #define RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED s2BIT(15)
608 #define RTI_DATA1_MEM_RX_TIMER_AC_EN s2BIT(38)
609 #define RTI_DATA1_MEM_RX_TIMER_CI_EN s2BIT(39)
621 #define RX_PA_CFG_IGNORE_FRM_ERR s2BIT(1)
622 #define RX_PA_CFG_IGNORE_SNAP_OUI s2BIT(2)
623 #define RX_PA_CFG_IGNORE_LLC_CTRL s2BIT(3)
624 #define RX_PA_CFG_IGNORE_L2_ERR s2BIT(6)
640 #define MAC_INT_STATUS_TMAC_INT s2BIT(0)
641 #define MAC_INT_STATUS_RMAC_INT s2BIT(1)
644 #define TMAC_ECC_SG_ERR s2BIT(7)
645 #define TMAC_ECC_DB_ERR s2BIT(15)
646 #define TMAC_TX_BUF_OVRN s2BIT(23)
647 #define TMAC_TX_CRI_ERR s2BIT(31)
648 #define TMAC_TX_SM_ERR s2BIT(39)
649 #define TMAC_DESC_ECC_SG_ERR s2BIT(47)
650 #define TMAC_DESC_ECC_DB_ERR s2BIT(55)
656 #define RMAC_RX_BUFF_OVRN s2BIT(0)
657 #define RMAC_FRM_RCVD_INT s2BIT(1)
658 #define RMAC_UNUSED_INT s2BIT(2)
659 #define RMAC_RTS_PNUM_ECC_SG_ERR s2BIT(5)
660 #define RMAC_RTS_DS_ECC_SG_ERR s2BIT(6)
661 #define RMAC_RD_BUF_ECC_SG_ERR s2BIT(7)
662 #define RMAC_RTH_MAP_ECC_SG_ERR s2BIT(8)
663 #define RMAC_RTH_SPDM_ECC_SG_ERR s2BIT(9)
664 #define RMAC_RTS_VID_ECC_SG_ERR s2BIT(10)
665 #define RMAC_DA_SHADOW_ECC_SG_ERR s2BIT(11)
666 #define RMAC_RTS_PNUM_ECC_DB_ERR s2BIT(13)
667 #define RMAC_RTS_DS_ECC_DB_ERR s2BIT(14)
668 #define RMAC_RD_BUF_ECC_DB_ERR s2BIT(15)
669 #define RMAC_RTH_MAP_ECC_DB_ERR s2BIT(16)
670 #define RMAC_RTH_SPDM_ECC_DB_ERR s2BIT(17)
671 #define RMAC_RTS_VID_ECC_DB_ERR s2BIT(18)
672 #define RMAC_DA_SHADOW_ECC_DB_ERR s2BIT(19)
673 #define RMAC_LINK_STATE_CHANGE_INT s2BIT(31)
674 #define RMAC_RX_SM_ERR s2BIT(39)
675 #define RMAC_SINGLE_ECC_ERR (s2BIT(5) | s2BIT(6) | s2BIT(7) |\
676 s2BIT(8) | s2BIT(9) | s2BIT(10)|\
677 s2BIT(11))
678 #define RMAC_DOUBLE_ECC_ERR (s2BIT(13) | s2BIT(14) | s2BIT(15) |\
679 s2BIT(16) | s2BIT(17) | s2BIT(18)|\
680 s2BIT(19))
687 #define MAC_CFG_TMAC_ENABLE s2BIT(0)
688 #define MAC_CFG_RMAC_ENABLE s2BIT(1)
689 #define MAC_CFG_LAN_NOT_WAN s2BIT(2)
690 #define MAC_CFG_TMAC_LOOPBACK s2BIT(3)
691 #define MAC_CFG_TMAC_APPEND_PAD s2BIT(4)
692 #define MAC_CFG_RMAC_STRIP_FCS s2BIT(5)
693 #define MAC_CFG_RMAC_STRIP_PAD s2BIT(6)
694 #define MAC_CFG_RMAC_PROM_ENABLE s2BIT(7)
695 #define MAC_RMAC_DISCARD_PFRM s2BIT(8)
696 #define MAC_RMAC_BCAST_ENABLE s2BIT(9)
697 #define MAC_RMAC_ALL_ADDR_ENABLE s2BIT(10)
709 #define RMAC_ERR_FCS s2BIT(0)
710 #define RMAC_ERR_FCS_ACCEPT s2BIT(1)
711 #define RMAC_ERR_TOO_LONG s2BIT(1)
712 #define RMAC_ERR_TOO_LONG_ACCEPT s2BIT(1)
713 #define RMAC_ERR_RUNT s2BIT(2)
714 #define RMAC_ERR_RUNT_ACCEPT s2BIT(2)
715 #define RMAC_ERR_LEN_MISMATCH s2BIT(3)
716 #define RMAC_ERR_LEN_MISMATCH_ACCEPT s2BIT(3)
733 #define RMAC_ADDR_CMD_MEM_WE s2BIT(7)
735 #define RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD s2BIT(15)
736 #define RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING s2BIT(15)
741 #define RMAC_ADDR_DATA0_MEM_USER s2BIT(48)
758 #define RMAC_PAUSE_GEN s2BIT(0)
759 #define RMAC_PAUSE_GEN_ENABLE s2BIT(0)
760 #define RMAC_PAUSE_RX s2BIT(1)
761 #define RMAC_PAUSE_RX_ENABLE s2BIT(1)
792 #define RTS_DIX_MAP_SCW(val) s2BIT(val,21)
798 #define RTS_CTRL_IGNORE_SNAP_OUI s2BIT(2)
799 #define RTS_CTRL_IGNORE_LLC_CTRL s2BIT(3)
802 #define RTS_PN_CAM_CTRL_WE s2BIT(7)
803 #define RTS_PN_CAM_CTRL_STROBE_NEW_CMD s2BIT(15)
804 #define RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED s2BIT(15)
807 #define RTS_PN_CAM_DATA_TCP_SELECT s2BIT(7)
812 #define RTS_DS_MEM_CTRL_WE s2BIT(7)
813 #define RTS_DS_MEM_CTRL_STROBE_NEW_CMD s2BIT(15)
814 #define RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED s2BIT(15)
828 #define MC_INT_STATUS_MC_INT s2BIT(0)
830 #define MC_INT_MASK_MC_INT s2BIT(0)
833 #define MC_ERR_REG_ECC_DB_ERR_L s2BIT(14)
834 #define MC_ERR_REG_ECC_DB_ERR_U s2BIT(15)
835 #define MC_ERR_REG_MIRI_ECC_DB_ERR_0 s2BIT(18)
836 #define MC_ERR_REG_MIRI_ECC_DB_ERR_1 s2BIT(20)
837 #define MC_ERR_REG_MIRI_CRI_ERR_0 s2BIT(22)
838 #define MC_ERR_REG_MIRI_CRI_ERR_1 s2BIT(23)
839 #define MC_ERR_REG_SM_ERR s2BIT(31)
840 #define MC_ERR_REG_ECC_ALL_SNG (s2BIT(2) | s2BIT(3) | s2BIT(4) | s2BIT(5) |\
841 s2BIT(17) | s2BIT(19))
842 #define MC_ERR_REG_ECC_ALL_DBL (s2BIT(10) | s2BIT(11) | s2BIT(12) |\
843 s2BIT(13) | s2BIT(18) | s2BIT(20))
844 #define PLL_LOCK_N s2BIT(39)
862 #define MC_RLDRAM_QUEUE_SIZE_ENABLE s2BIT(39)
863 #define MC_RLDRAM_MRS_ENABLE s2BIT(47)
876 #define MC_RLDRAM_TEST_MODE s2BIT(47)
877 #define MC_RLDRAM_TEST_WRITE s2BIT(7)
878 #define MC_RLDRAM_TEST_GO s2BIT(15)
879 #define MC_RLDRAM_TEST_DONE s2BIT(23)
880 #define MC_RLDRAM_TEST_PASS s2BIT(31)
893 #define MC_RLDRAM_ENABLE_ODT s2BIT(7)
911 #define XGXS_INT_STATUS_TXGXS s2BIT(0)
912 #define XGXS_INT_STATUS_RXGXS s2BIT(1)
914 #define XGXS_INT_MASK_TXGXS s2BIT(0)
915 #define XGXS_INT_MASK_RXGXS s2BIT(1)
918 #define TXGXS_ECC_SG_ERR s2BIT(7)
919 #define TXGXS_ECC_DB_ERR s2BIT(15)
920 #define TXGXS_ESTORE_UFLOW s2BIT(31)
921 #define TXGXS_TX_SM_ERR s2BIT(39)
927 #define RXGXS_ESTORE_OFLOW s2BIT(7)
928 #define RXGXS_RX_SM_ERR s2BIT(39)
947 #define SPI_CONTROL_SEL1 s2BIT(4)
948 #define SPI_CONTROL_REQ s2BIT(7)
949 #define SPI_CONTROL_NACK s2BIT(5)
950 #define SPI_CONTROL_DONE s2BIT(6)