Lines Matching refs:iobase
89 static int w83977af_open(int i, unsigned int iobase, unsigned int irq,
92 static int w83977af_probe(int iobase, int irq, int dma);
97 static int w83977af_pio_write(int iobase, __u8 *buf, int len, int fifo_size);
98 static void w83977af_dma_write(struct w83977af_ir *self, int iobase);
156 static int w83977af_open(int i, unsigned int iobase, unsigned int irq, in w83977af_open() argument
166 if (!request_region(iobase, CHIP_IO_EXTENT, driver_name)) { in w83977af_open()
168 __func__ , iobase); in w83977af_open()
172 if (w83977af_probe(iobase, irq, dma) == -1) { in w83977af_open()
192 self->io.fir_base = iobase; in w83977af_open()
263 release_region(iobase, CHIP_IO_EXTENT); in w83977af_open()
275 int iobase; in w83977af_close() local
279 iobase = self->io.fir_base; in w83977af_close()
314 static int w83977af_probe(int iobase, int irq, int dma) in w83977af_probe() argument
328 w977_write_reg(0x60, (iobase >> 8) & 0xff, efbase[i]); in w83977af_probe()
329 w977_write_reg(0x61, (iobase) & 0xff, efbase[i]); in w83977af_probe()
349 switch_bank(iobase, SET2); in w83977af_probe()
350 outb(iobase+2, 0x00); in w83977af_probe()
353 switch_bank(iobase, SET0); in w83977af_probe()
354 outb(HCR_EN_IRQ, iobase+HCR); in w83977af_probe()
357 switch_bank(iobase, SET2); in w83977af_probe()
358 outb(inb(iobase+ADCR1) | ADCR1_ADV_SL, iobase+ADCR1); in w83977af_probe()
361 switch_bank(iobase, SET0); in w83977af_probe()
362 outb(HCR_SIR, iobase+HCR); in w83977af_probe()
365 switch_bank(iobase, SET3); in w83977af_probe()
366 version = inb(iobase+AUID); in w83977af_probe()
373 switch_bank(iobase, SET2); in w83977af_probe()
374 outb(ADCR2_RXFS32|ADCR2_TXFS32, iobase+ADCR2); in w83977af_probe()
377 switch_bank(iobase, SET0); in w83977af_probe()
379 UFR_EN_FIFO,iobase+UFR); in w83977af_probe()
382 switch_bank(iobase, SET4); in w83977af_probe()
383 outb(2048 & 0xff, iobase+6); in w83977af_probe()
384 outb((2048 >> 8) & 0x1f, iobase+7); in w83977af_probe()
398 switch_bank(iobase, SET7); in w83977af_probe()
399 outb(0x40, iobase+7); in w83977af_probe()
416 int iobase; in w83977af_change_speed() local
419 iobase = self->io.fir_base; in w83977af_change_speed()
425 set = inb(iobase+SSR); in w83977af_change_speed()
428 switch_bank(iobase, SET0); in w83977af_change_speed()
429 outb(0, iobase+ICR); in w83977af_change_speed()
432 switch_bank(iobase, SET2); in w83977af_change_speed()
433 outb(0x00, iobase+ABHL); in w83977af_change_speed()
436 case 9600: outb(0x0c, iobase+ABLL); break; in w83977af_change_speed()
437 case 19200: outb(0x06, iobase+ABLL); break; in w83977af_change_speed()
438 case 38400: outb(0x03, iobase+ABLL); break; in w83977af_change_speed()
439 case 57600: outb(0x02, iobase+ABLL); break; in w83977af_change_speed()
440 case 115200: outb(0x01, iobase+ABLL); break; in w83977af_change_speed()
460 switch_bank(iobase, SET0); in w83977af_change_speed()
461 outb(ir_mode, iobase+HCR); in w83977af_change_speed()
464 switch_bank(iobase, SET2); in w83977af_change_speed()
465 outb(ADCR2_RXFS32|ADCR2_TXFS32, iobase+ADCR2); in w83977af_change_speed()
468 switch_bank(iobase, SET0); in w83977af_change_speed()
469 outb(0x00, iobase+UFR); /* Reset */ in w83977af_change_speed()
470 outb(UFR_EN_FIFO, iobase+UFR); /* First we must enable FIFO */ in w83977af_change_speed()
471 outb(0xa7, iobase+UFR); in w83977af_change_speed()
476 switch_bank(iobase, SET0); in w83977af_change_speed()
478 outb(ICR_EFSFI, iobase+ICR); in w83977af_change_speed()
481 outb(ICR_ERBRI, iobase+ICR); in w83977af_change_speed()
484 outb(set, iobase+SSR); in w83977af_change_speed()
498 int iobase; in w83977af_hard_xmit() local
504 iobase = self->io.fir_base; in w83977af_hard_xmit()
525 set = inb(iobase+SSR); in w83977af_hard_xmit()
539 switch_bank(iobase, SET0); in w83977af_hard_xmit()
540 outb(ICR_EDMAI, iobase+ICR); in w83977af_hard_xmit()
541 w83977af_dma_write(self, iobase); in w83977af_hard_xmit()
548 switch_bank(iobase, SET0); in w83977af_hard_xmit()
549 outb(ICR_ETXTHI, iobase+ICR); in w83977af_hard_xmit()
554 outb(set, iobase+SSR); in w83977af_hard_xmit()
565 static void w83977af_dma_write(struct w83977af_ir *self, int iobase) in w83977af_dma_write() argument
575 set = inb(iobase+SSR); in w83977af_dma_write()
578 switch_bank(iobase, SET0); in w83977af_dma_write()
579 outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR); in w83977af_dma_write()
582 switch_bank(iobase, SET2); in w83977af_dma_write()
583 outb(ADCR1_D_CHSW|/*ADCR1_DMA_F|*/ADCR1_ADV_SL, iobase+ADCR1); in w83977af_dma_write()
599 switch_bank(iobase, SET0); in w83977af_dma_write()
601 hcr = inb(iobase+HCR); in w83977af_dma_write()
602 outb(hcr | HCR_EN_DMA, iobase+HCR); in w83977af_dma_write()
606 outb(inb(iobase+HCR) | HCR_EN_DMA | HCR_TX_WT, iobase+HCR); in w83977af_dma_write()
610 outb(set, iobase+SSR); in w83977af_dma_write()
619 static int w83977af_pio_write(int iobase, __u8 *buf, int len, int fifo_size) in w83977af_pio_write() argument
627 set = inb(iobase+SSR); in w83977af_pio_write()
629 switch_bank(iobase, SET0); in w83977af_pio_write()
630 if (!(inb_p(iobase+USR) & USR_TSRE)) { in w83977af_pio_write()
642 outb(buf[actual++], iobase+TBR); in w83977af_pio_write()
649 outb(set, iobase+SSR); in w83977af_pio_write()
663 int iobase; in w83977af_dma_xmit_complete() local
670 iobase = self->io.fir_base; in w83977af_dma_xmit_complete()
673 set = inb(iobase+SSR); in w83977af_dma_xmit_complete()
676 switch_bank(iobase, SET0); in w83977af_dma_xmit_complete()
677 outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR); in w83977af_dma_xmit_complete()
680 if (inb(iobase+AUDR) & AUDR_UNDR) { in w83977af_dma_xmit_complete()
687 outb(AUDR_UNDR, iobase+AUDR); in w83977af_dma_xmit_complete()
702 outb(set, iobase+SSR); in w83977af_dma_xmit_complete()
714 int iobase; in w83977af_dma_receive() local
724 iobase= self->io.fir_base; in w83977af_dma_receive()
727 set = inb(iobase+SSR); in w83977af_dma_receive()
730 switch_bank(iobase, SET0); in w83977af_dma_receive()
731 outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR); in w83977af_dma_receive()
734 switch_bank(iobase, SET2); in w83977af_dma_receive()
735 outb((inb(iobase+ADCR1) & ~ADCR1_D_CHSW)/*|ADCR1_DMA_F*/|ADCR1_ADV_SL, in w83977af_dma_receive()
736 iobase+ADCR1); in w83977af_dma_receive()
758 switch_bank(iobase, SET0); in w83977af_dma_receive()
759 outb(UFR_RXTL|UFR_TXTL|UFR_RXF_RST|UFR_EN_FIFO, iobase+UFR); in w83977af_dma_receive()
763 switch_bank(iobase, SET0); in w83977af_dma_receive()
765 hcr = inb(iobase+HCR); in w83977af_dma_receive()
766 outb(hcr | HCR_EN_DMA, iobase+HCR); in w83977af_dma_receive()
770 outb(inb(iobase+HCR) | HCR_EN_DMA, iobase+HCR); in w83977af_dma_receive()
773 outb(set, iobase+SSR); in w83977af_dma_receive()
789 int iobase; in w83977af_dma_receive_complete() local
797 iobase = self->io.fir_base; in w83977af_dma_receive_complete()
800 set = inb(iobase+SSR); in w83977af_dma_receive_complete()
802 iobase = self->io.fir_base; in w83977af_dma_receive_complete()
805 switch_bank(iobase, SET5); in w83977af_dma_receive_complete()
806 while ((status = inb(iobase+FS_FO)) & FS_FO_FSFDR) { in w83977af_dma_receive_complete()
809 st_fifo->entries[st_fifo->tail].len = inb(iobase+RFLFL); in w83977af_dma_receive_complete()
810 st_fifo->entries[st_fifo->tail].len |= inb(iobase+RFLFH) << 8; in w83977af_dma_receive_complete()
852 switch_bank(iobase, SET0); in w83977af_dma_receive_complete()
853 if (inb(iobase+USR) & USR_RDR) { in w83977af_dma_receive_complete()
862 outb(set, iobase+SSR); in w83977af_dma_receive_complete()
894 outb(set, iobase+SSR); in w83977af_dma_receive_complete()
908 int iobase; in w83977af_pio_receive() local
914 iobase = self->io.fir_base; in w83977af_pio_receive()
918 byte = inb(iobase+RBR); in w83977af_pio_receive()
921 } while (inb(iobase+USR) & USR_RDR); /* Data available */ in w83977af_pio_receive()
935 int iobase; in w83977af_sir_interrupt() local
939 iobase = self->io.fir_base; in w83977af_sir_interrupt()
957 set = inb(iobase+SSR); in w83977af_sir_interrupt()
958 switch_bank(iobase, SET0); in w83977af_sir_interrupt()
959 outb(AUDR_SFEND, iobase+AUDR); in w83977af_sir_interrupt()
960 outb(set, iobase+SSR); in w83977af_sir_interrupt()
1004 int iobase; in w83977af_fir_interrupt() local
1006 iobase = self->io.fir_base; in w83977af_fir_interrupt()
1007 set = inb(iobase+SSR); in w83977af_fir_interrupt()
1019 switch_bank(iobase, SET4); in w83977af_fir_interrupt()
1020 outb(0x01, iobase+TMRL); /* 1 ms */ in w83977af_fir_interrupt()
1021 outb(0x00, iobase+TMRH); in w83977af_fir_interrupt()
1024 outb(IR_MSL_EN_TMR, iobase+IR_MSL); in w83977af_fir_interrupt()
1032 switch_bank(iobase, SET4); in w83977af_fir_interrupt()
1033 outb(0, iobase+IR_MSL); in w83977af_fir_interrupt()
1041 w83977af_dma_write(self, iobase); in w83977af_fir_interrupt()
1068 outb(set, iobase+SSR); in w83977af_fir_interrupt()
1084 int iobase; in w83977af_interrupt() local
1088 iobase = self->io.fir_base; in w83977af_interrupt()
1091 set = inb(iobase+SSR); in w83977af_interrupt()
1092 switch_bank(iobase, SET0); in w83977af_interrupt()
1094 icr = inb(iobase+ICR); in w83977af_interrupt()
1095 isr = inb(iobase+ISR) & icr; /* Mask out the interesting ones */ in w83977af_interrupt()
1097 outb(0, iobase+ICR); /* Disable interrupts */ in w83977af_interrupt()
1107 outb(icr, iobase+ICR); /* Restore (new) interrupts */ in w83977af_interrupt()
1108 outb(set, iobase+SSR); /* Restore bank register */ in w83977af_interrupt()
1121 int iobase; in w83977af_is_receiving() local
1127 iobase = self->io.fir_base; in w83977af_is_receiving()
1130 set = inb(iobase+SSR); in w83977af_is_receiving()
1131 switch_bank(iobase, SET2); in w83977af_is_receiving()
1132 if ((inb(iobase+RXFDTH) & 0x3f) != 0) { in w83977af_is_receiving()
1136 outb(set, iobase+SSR); in w83977af_is_receiving()
1152 int iobase; in w83977af_net_open() local
1163 iobase = self->io.fir_base; in w83977af_net_open()
1179 set = inb(iobase+SSR); in w83977af_net_open()
1182 switch_bank(iobase, SET0); in w83977af_net_open()
1184 outb(ICR_EFSFI, iobase+ICR); in w83977af_net_open()
1187 outb(ICR_ERBRI, iobase+ICR); in w83977af_net_open()
1190 outb(set, iobase+SSR); in w83977af_net_open()
1216 int iobase; in w83977af_net_close() local
1227 iobase = self->io.fir_base; in w83977af_net_close()
1240 set = inb(iobase+SSR); in w83977af_net_close()
1243 switch_bank(iobase, SET0); in w83977af_net_close()
1244 outb(0, iobase+ICR); in w83977af_net_close()
1250 outb(set, iobase+SSR); in w83977af_net_close()