182 iow(board_info_t * db, int reg, int value)  in iow()  function
373 	iow(db, DM9000_EPAR, offset);  in dm9000_read_eeprom()
374 	iow(db, DM9000_EPCR, EPCR_ERPRR);  in dm9000_read_eeprom()
385 	iow(db, DM9000_EPCR, 0x0);  in dm9000_read_eeprom()
409 	iow(db, DM9000_EPAR, offset);  in dm9000_write_eeprom()
410 	iow(db, DM9000_EPDRH, data[1]);  in dm9000_write_eeprom()
411 	iow(db, DM9000_EPDRL, data[0]);  in dm9000_write_eeprom()
412 	iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW);  in dm9000_write_eeprom()
420 	iow(db, DM9000_EPCR, 0);  in dm9000_write_eeprom()
485 		iow(dm, DM9000_RCSR, dm->rx_csum ? RCSR_CSUM : 0);  in dm9000_set_rx_csum_unlocked()
615 	iow(dm, DM9000_WCR, wcr);  in dm9000_set_wol()
746 		iow(db, oft, dev->dev_addr[i]);  in dm9000_hash_table_unlocked()
769 		iow(db, oft++, hash_table[i]);  in dm9000_hash_table_unlocked()
770 		iow(db, oft++, hash_table[i] >> 8);  in dm9000_hash_table_unlocked()
773 	iow(db, DM9000_RCR, rcr);  in dm9000_hash_table_unlocked()
805 	iow(db, DM9000_GPCR, GPCR_GEP_CNTL);	/* Let GPIO0 output */  in dm9000_init_dm9000()
815 	iow(db, DM9000_NCR, ncr);  in dm9000_init_dm9000()
818 	iow(db, DM9000_TCR, 0);	        /* TX Polling clear */  in dm9000_init_dm9000()
819 	iow(db, DM9000_BPTR, 0x3f);	/* Less 3Kb, 200us */  in dm9000_init_dm9000()
820 	iow(db, DM9000_FCR, 0xff);	/* Flow Control */  in dm9000_init_dm9000()
821 	iow(db, DM9000_SMCR, 0);        /* Special Mode */  in dm9000_init_dm9000()
823 	iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);  in dm9000_init_dm9000()
824 	iow(db, DM9000_ISR, ISR_CLR_STATUS); /* Clear interrupt status */  in dm9000_init_dm9000()
836 	iow(db, DM9000_IMR, imr);  in dm9000_init_dm9000()
876 			iow(dm, DM9000_TCCR, 0);  in dm9000_send_packet()
878 			iow(dm, DM9000_TCCR, TCCR_IP | TCCR_UDP | TCCR_TCP);  in dm9000_send_packet()
883 	iow(dm, DM9000_TXPLL, pkt_len);  in dm9000_send_packet()
884 	iow(dm, DM9000_TXPLH, pkt_len >> 8);  in dm9000_send_packet()
887 	iow(dm, DM9000_TCR, TCR_TXREQ);	/* Cleared after TX complete */  in dm9000_send_packet()
986 			iow(db, DM9000_RCR, 0x00);	/* Stop Device */  in dm9000_rx()
987 			iow(db, DM9000_ISR, IMR_PAR);	/* Stop INT request */  in dm9000_rx()
1088 	iow(db, DM9000_IMR, IMR_PAR);  in dm9000_interrupt()
1092 	iow(db, DM9000_ISR, int_status);	/* Clear ISR status */  in dm9000_interrupt()
1113 	iow(db, DM9000_IMR, db->imr_all);  in dm9000_interrupt()
1139 		iow(db, DM9000_NSR, NSR_WAKEST);  in dm9000_wol_interrupt()
1195 	iow(db, DM9000_GPR, 0);	/* REG_1F bit0 activate phyxcer */  in dm9000_open()
1244 	iow(db, DM9000_EPAR, DM9000_PHY | reg);  in dm9000_phy_read()
1246 	iow(db, DM9000_EPCR, EPCR_ERPRR | EPCR_EPOS);	/* Issue phyxcer read command */  in dm9000_phy_read()
1256 	iow(db, DM9000_EPCR, 0x0);	/* Clear phyxcer read command */  in dm9000_phy_read()
1291 	iow(db, DM9000_EPAR, DM9000_PHY | reg);  in dm9000_phy_write()
1294 	iow(db, DM9000_EPDRL, value);  in dm9000_phy_write()
1295 	iow(db, DM9000_EPDRH, value >> 8);  in dm9000_phy_write()
1297 	iow(db, DM9000_EPCR, EPCR_EPOS | EPCR_ERPRW);	/* Issue phyxcer write command */  in dm9000_phy_write()
1307 	iow(db, DM9000_EPCR, 0x0);	/* Clear phyxcer write command */  in dm9000_phy_write()
1323 	iow(db, DM9000_GPR, 0x01);	/* Power-Down PHY */  in dm9000_shutdown()
1324 	iow(db, DM9000_IMR, IMR_PAR);	/* Disable all interrupt */  in dm9000_shutdown()
1325 	iow(db, DM9000_RCR, 0x00);	/* Disable RX */  in dm9000_shutdown()