730 		row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +  in bnx2x_mc_assert()
732 		row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +  in bnx2x_mc_assert()
734 		row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +  in bnx2x_mc_assert()
736 		row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +  in bnx2x_mc_assert()
758 		row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +  in bnx2x_mc_assert()
760 		row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +  in bnx2x_mc_assert()
762 		row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +  in bnx2x_mc_assert()
764 		row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +  in bnx2x_mc_assert()
786 		row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +  in bnx2x_mc_assert()
788 		row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +  in bnx2x_mc_assert()
790 		row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +  in bnx2x_mc_assert()
792 		row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +  in bnx2x_mc_assert()
814 		row0 = REG_RD(bp, BAR_USTRORM_INTMEM +  in bnx2x_mc_assert()
816 		row1 = REG_RD(bp, BAR_USTRORM_INTMEM +  in bnx2x_mc_assert()
818 		row2 = REG_RD(bp, BAR_USTRORM_INTMEM +  in bnx2x_mc_assert()
820 		row3 = REG_RD(bp, BAR_USTRORM_INTMEM +  in bnx2x_mc_assert()
853 	mark = REG_RD(bp, addr);  in bnx2x_fw_dump()
861 			data[word] = htonl(REG_RD(bp, offset + 4*word));  in bnx2x_fw_dump()
867 			data[word] = htonl(REG_RD(bp, offset + 4*word));  in bnx2x_fw_dump()
907 		*((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +  in bnx2x_panic_dump()
987 			*(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +  in bnx2x_panic_dump()
1099 	u32 val = REG_RD(bp, addr);  in bnx2x_hc_int_enable()
1166 	val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);  in bnx2x_igu_int_enable()
1223 	u32 val = REG_RD(bp, addr);  in bnx2x_hc_int_disable()
1253 	if (REG_RD(bp, addr) != val)  in bnx2x_hc_int_disable()
1259 	u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);  in bnx2x_igu_int_disable()
1271 	if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)  in bnx2x_igu_int_disable()
1345 	lock_status = REG_RD(bp, hw_lock_control_reg);  in bnx2x_trylock_hw_lock()
1502 	lock_status = REG_RD(bp, hw_lock_control_reg);  in bnx2x_acquire_hw_lock()
1513 		lock_status = REG_RD(bp, hw_lock_control_reg);  in bnx2x_acquire_hw_lock()
1548 	lock_status = REG_RD(bp, hw_lock_control_reg);  in bnx2x_release_hw_lock()
1563 	int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&  in bnx2x_get_gpio()
1564 			 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;  in bnx2x_get_gpio()
1577 	gpio_reg = REG_RD(bp, MISC_REG_GPIO);  in bnx2x_get_gpio()
1593 	int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&  in bnx2x_set_gpio()
1594 			 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;  in bnx2x_set_gpio()
1607 	gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);  in bnx2x_set_gpio()
1646 	int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&  in bnx2x_set_gpio_int()
1647 			 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;  in bnx2x_set_gpio_int()
1660 	gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);  in bnx2x_set_gpio_int()
1702 	spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);  in bnx2x_set_spio()
2817 		val = REG_RD(bp, GRCBASE_MCP + 0x9c);  in bnx2x_acquire_alr()
2880 	aeu_mask = REG_RD(bp, aeu_addr);  in bnx2x_attn_int_asserted()
2900 			nig_mask = REG_RD(bp, nig_int_mask_addr);  in bnx2x_attn_int_asserted()
2997 		val = REG_RD(bp, reg_offset);  in bnx2x_attn_int_deasserted0()
3017 		val = REG_RD(bp, reg_offset);  in bnx2x_attn_int_deasserted0()
3033 		val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);  in bnx2x_attn_int_deasserted1()
3048 		val = REG_RD(bp, reg_offset);  in bnx2x_attn_int_deasserted1()
3064 		val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);  in bnx2x_attn_int_deasserted2()
3073 		val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);  in bnx2x_attn_int_deasserted2()
3079 			val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);  in bnx2x_attn_int_deasserted2()
3092 		val = REG_RD(bp, reg_offset);  in bnx2x_attn_int_deasserted2()
3156 					REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);  in bnx2x_attn_int_deasserted3()
3161 					REG_RD(bp, MISC_REG_GRC_RSV_ATTN);  in bnx2x_attn_int_deasserted3()
3179 	u32 val	= REG_RD(bp, BNX2X_MISC_GEN_REG);  in bnx2x_set_reset_done()
3191 	u32 val	= REG_RD(bp, BNX2X_MISC_GEN_REG);  in bnx2x_set_reset_in_progress()
3203 	u32 val	= REG_RD(bp, BNX2X_MISC_GEN_REG);  in bnx2x_reset_is_done()
3213 	u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);  in bnx2x_inc_load_cnt()
3228 	u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);  in bnx2x_dec_load_cnt()
3245 	return REG_RD(bp, BNX2X_MISC_GEN_REG) & LOAD_COUNTER_MASK;  in bnx2x_get_load_cnt()
3250 	u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);  in bnx2x_clear_load_cnt()
3449 	attn.sig[0] = REG_RD(bp,  in bnx2x_chk_parity_attn()
3452 	attn.sig[1] = REG_RD(bp,  in bnx2x_chk_parity_attn()
3455 	attn.sig[2] = REG_RD(bp,  in bnx2x_chk_parity_attn()
3458 	attn.sig[3] = REG_RD(bp,  in bnx2x_chk_parity_attn()
3472 		val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);  in bnx2x_attn_int_deasserted4()
3505 		val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);  in bnx2x_attn_int_deasserted4()
3560 	attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);  in bnx2x_attn_int_deasserted()
3561 	attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);  in bnx2x_attn_int_deasserted()
3562 	attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);  in bnx2x_attn_int_deasserted()
3563 	attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);  in bnx2x_attn_int_deasserted()
3566 		      REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);  in bnx2x_attn_int_deasserted()
3617 	aeu_mask = REG_RD(bp, reg_addr);  in bnx2x_attn_int_deasserted()
4173 			   REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);  in bnx2x_init_def_sb()
4181 			bp->attn_group[index].sig[4] = REG_RD(bp,  in bnx2x_init_def_sb()
4524 		REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &  in bnx2x_nic_init()
4700 		val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);  in bnx2x_int_mem_test()
4754 	val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);  in bnx2x_int_mem_test()
4764 	val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);  in bnx2x_int_mem_test()
4770 		REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);  in bnx2x_int_mem_test()
4771 	val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);  in bnx2x_int_mem_test()
4925 	val = REG_RD(bp, MISC_REG_SPIO_INT);  in bnx2x_setup_fan_failure_detection()
4931 	val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);  in bnx2x_setup_fan_failure_detection()
4975 	REG_RD(bp, offset);  in bnx2x_pretend_func()
4981 	u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);  in bnx2x_pf_disable()
5062 	val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);  in bnx2x_init_hw_common()
5067 	val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);  in bnx2x_init_hw_common()
5123 			val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);  in bnx2x_init_hw_common()
5346 	REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);  in bnx2x_init_hw_common()
5550 		val = REG_RD(bp, reg_addr);  in bnx2x_init_hw_port()
5598 		val = REG_RD(bp, addr);  in bnx2x_init_hw_func()
5847 		val = REG_RD(bp, main_mem_prty_clr);  in bnx2x_init_hw_func()
5862 		REG_RD(bp, main_mem_prty_clr);  in bnx2x_init_hw_func()
7106 		if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))  in bnx2x_reset_func()
7152 	val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);  in bnx2x_reset_port()
7347 		val = REG_RD(bp, addr);  in bnx2x_disable_close_the_gate()
7351 		val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);  in bnx2x_disable_close_the_gate()
7366 		val = REG_RD(bp, PXP_REG_HST_DISCARD_DOORBELLS);  in bnx2x_set_234_gates()
7370 		val = REG_RD(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES);  in bnx2x_set_234_gates()
7377 	val = REG_RD(bp, addr);  in bnx2x_set_234_gates()
7426 	shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);  in bnx2x_reset_mcp_prep()
7460 	shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);  in bnx2x_reset_mcp_comp()
7474 		val = REG_RD(bp, shmem + validity_offset);  in bnx2x_reset_mcp_comp()
7572 		sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);  in bnx2x_process_kill()
7573 		blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);  in bnx2x_process_kill()
7574 		port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);  in bnx2x_process_kill()
7575 		port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);  in bnx2x_process_kill()
7576 		pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);  in bnx2x_process_kill()
7823 	REG_RD(bp, reg);	/* Flush the GRC transaction (in the chip) */  in bnx2x_undi_int_disable_e1h()
7833 	REG_RD(bp, reg);  in bnx2x_undi_int_disable_e1h()
7849 	val = REG_RD(bp, MISC_REG_UNPREPARED);  in bnx2x_undi_unload()
7855 		val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);  in bnx2x_undi_unload()
7914 			swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);  in bnx2x_undi_unload()
7915 			swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);  in bnx2x_undi_unload()
7950 	val = REG_RD(bp, MISC_REG_CHIP_NUM);  in bnx2x_get_common_hwinfo()
7952 	val = REG_RD(bp, MISC_REG_CHIP_REV);  in bnx2x_get_common_hwinfo()
7954 	val = REG_RD(bp, MISC_REG_CHIP_METAL);  in bnx2x_get_common_hwinfo()
7956 	val = REG_RD(bp, MISC_REG_BOND_ID);  in bnx2x_get_common_hwinfo()
7964 		val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);  in bnx2x_get_common_hwinfo()
7966 			val = REG_RD(bp, MISC_REG_PORT4MODE_EN);  in bnx2x_get_common_hwinfo()
7996 	val = (REG_RD(bp, 0x2874) & 0x55);  in bnx2x_get_common_hwinfo()
8003 	val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);  in bnx2x_get_common_hwinfo()
8009 	bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);  in bnx2x_get_common_hwinfo()
8010 	bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?  in bnx2x_get_common_hwinfo()
8110 		val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);  in bnx2x_get_igu_cam_info()
8179 		bp->port.phy_addr = REG_RD(bp, NIG_REG_SERDES0_CTRL_PHY_ADDR +  in bnx2x_link_settings_supported()
8185 		bp->port.phy_addr = REG_RD(bp, NIG_REG_XGXS0_CTRL_PHY_ADDR +  in bnx2x_link_settings_supported()
8653 		val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);  in bnx2x_get_hwinfo()
9487 	u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);  in bnx2x_get_pcie_width_speed()
9931 	bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);  in bnx2x_eeh_recover()