Lines Matching refs:REG_RD
188 u32 val = REG_RD(bp, reg); in bnx2x_bits_en()
197 u32 val = REG_RD(bp, reg); in bnx2x_bits_dis()
422 val_xoff = REG_RD(bp, emac_base + in bnx2x_emac_get_pfc_stat()
425 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD); in bnx2x_emac_get_pfc_stat()
431 val_xoff = REG_RD(bp, emac_base + in bnx2x_emac_get_pfc_stat()
434 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT); in bnx2x_emac_get_pfc_stat()
452 val = REG_RD(bp, MISC_REG_RESET_REG_2); in bnx2x_pfc_statistic()
485 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); in bnx2x_emac_init()
490 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); in bnx2x_emac_init()
549 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); in bnx2x_emac_enable()
577 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); in bnx2x_emac_enable()
607 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); in bnx2x_emac_enable()
873 xcm_mask = REG_RD(bp, in bnx2x_update_pfc_nig()
983 val = REG_RD(bp, MISC_REG_RESET_REG_2); in bnx2x_update_pfc()
1191 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4); in bnx2x_bmac_rx_disable()
1194 if (REG_RD(bp, MISC_REG_RESET_REG_2) & in bnx2x_bmac_rx_disable()
1233 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4); in bnx2x_pbf_update()
1234 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); in bnx2x_pbf_update()
1240 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); in bnx2x_pbf_update()
1243 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); in bnx2x_pbf_update()
1329 if (REG_RD(bp, NIG_REG_PORT_SWAP)) in bnx2x_get_emac_base()
1335 if (REG_RD(bp, NIG_REG_PORT_SWAP)) in bnx2x_get_emac_base()
1366 saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); in bnx2x_cl45_write()
1372 REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); in bnx2x_cl45_write()
1385 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl45_write()
1405 tmp = REG_RD(bp, phy->mdio_ctrl + in bnx2x_cl45_write()
1436 saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); in bnx2x_cl45_read()
1442 REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); in bnx2x_cl45_read()
1454 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl45_read()
1476 val = REG_RD(bp, phy->mdio_ctrl + in bnx2x_cl45_read()
1624 vars->link_status = REG_RD(bp, params->shmem_base + in bnx2x_link_status_update()
2877 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); in bnx2x_link_int_enable()
2879 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), in bnx2x_link_int_enable()
2880 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), in bnx2x_link_int_enable()
2881 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c)); in bnx2x_link_int_enable()
2883 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), in bnx2x_link_int_enable()
2884 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); in bnx2x_link_int_enable()
2898 latch_status = REG_RD(bp, in bnx2x_rearm_latch_signal()
3037 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr); in bnx2x_get_ext_phy_fw_version()
3047 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr); in bnx2x_get_ext_phy_fw_version()
3075 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + in bnx2x_set_xgxs_loopback()
3479 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); in bnx2x_link_update()
3481 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + in bnx2x_link_update()
3484 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), in bnx2x_link_update()
3486 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); in bnx2x_link_update()
3489 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), in bnx2x_link_update()
3490 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); in bnx2x_link_update()
4116 if (REG_RD(bp, params->shmem_base + in bnx2x_8073_config_init()
4444 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); in bnx2x_get_gpio_port()
4445 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); in bnx2x_get_gpio_port()
4458 tx_en_mode = REG_RD(bp, params->shmem_base + in bnx2x_sfp_set_transmitter()
4769 val = REG_RD(bp, params->shmem_base + in bnx2x_verify_sfp_module()
4999 u32 fault_led_gpio = REG_RD(bp, params->shmem_base + in bnx2x_set_sfp_module_fault_led()
5033 u32 val = REG_RD(bp, params->shmem_base + in bnx2x_sfp_module_detection()
5115 u32 val = REG_RD(bp, params->shmem_base + in bnx2x_handle_module_detect_int()
5269 tx_en_mode = REG_RD(bp, params->shmem_base + in bnx2x_8706_config_init()
5453 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); in bnx2x_8726_config_init()
5454 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); in bnx2x_8726_config_init()
5468 val = REG_RD(bp, offset); in bnx2x_8726_config_init()
5546 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); in bnx2x_8727_hw_reset()
5547 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); in bnx2x_8727_hw_reset()
5699 tx_en_mode = REG_RD(bp, params->shmem_base + in bnx2x_8727_config_init()
5723 u32 val = REG_RD(bp, params->shmem_base + in bnx2x_8727_handle_mod_abs()
6300 cms_enable = REG_RD(bp, params->shmem_base + in bnx2x_848x3_config_init()
7217 rx = REG_RD(bp, shmem_base + in bnx2x_populate_preemphasis()
7221 tx = REG_RD(bp, shmem_base + in bnx2x_populate_preemphasis()
7225 rx = REG_RD(bp, shmem_base + in bnx2x_populate_preemphasis()
7229 tx = REG_RD(bp, shmem_base + in bnx2x_populate_preemphasis()
7248 ext_phy_config = REG_RD(bp, shmem_base + in bnx2x_get_ext_phy_config()
7253 ext_phy_config = REG_RD(bp, shmem_base + in bnx2x_get_ext_phy_config()
7269 u32 switch_cfg = (REG_RD(bp, shmem_base + in bnx2x_populate_int_phy()
7273 chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16; in bnx2x_populate_int_phy()
7276 phy_addr = REG_RD(bp, in bnx2x_populate_int_phy()
7282 phy_addr = REG_RD(bp, in bnx2x_populate_int_phy()
7373 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region, in bnx2x_populate_ext_phy()
7384 u32 size = REG_RD(bp, shmem2_base); in bnx2x_populate_ext_phy()
7435 link_config = REG_RD(bp, params->shmem_base + in bnx2x_phy_def_cfg()
7438 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + in bnx2x_phy_def_cfg()
7443 link_config = REG_RD(bp, params->shmem_base + in bnx2x_phy_def_cfg()
7446 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + in bnx2x_phy_def_cfg()
7823 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); in bnx2x_8073_common_init_phy()
7824 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); in bnx2x_8073_common_init_phy()
7948 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); in bnx2x_8726_common_init_phy()
7991 u32 phy_gpio_reset = REG_RD(bp, shmem_base + in bnx2x_get_ext_phy_reset_gpio()
8042 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); in bnx2x_8727_common_init_phy()
8043 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); in bnx2x_8727_common_init_phy()
8184 phy_ver = REG_RD(bp, shmem_base_path[0] + in bnx2x_common_init_phy()